NAND Flash Memory Page Buffer Bit Line Select Gate Architecture
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Solution Overview
Problem
The limitations of traditional NAND flash memory architectures, where the number of page buffers is limited due to their large circuit size, restrict the read/write performance, as each page buffer can only connect to one or two bit lines, limiting data throughput.
Innovation Solution
The introduction of bit line select gates that allow a page buffer to connect to multiple bit lines, enabling simultaneous programming and reading of multiple bit lines, along with additional pass gates and data registers to enhance operation, thereby increasing data throughput without increasing the number of page buffers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of page buffers is increased to improve read/write throughput, then data read/write throughput is improved, but device complexity and die size increase since page buffers occupy 20% to 40% of the memory's die size
Solution Approach 1:
The patent segments the connection between page buffers and bit lines by introducing bit line select gates. Instead of directly connecting each page buffer to multiple bit lines, the select gates act as intermediate segments that enable one page buffer to serve multiple bit lines sequentially. This segmentation allows the system to achieve multi-bit line operation without proportionally increasing page buffer count, thereby improving throughput while controlling complexity.
Solution Approach 2:
The patent makes page buffers multi-functional by enabling a single page buffer to connect to and operate on multiple bit lines through the bit line select gates. This universality allows one page buffer to perform the function of multiple page buffers would traditionally require, effectively increasing throughput without linearly increasing the number of page buffers and associated complexity.
2Device complexity
If each page buffer is connected to only one or two bit lines to simplify the architecture, then device complexity is reduced, but productivity decreases since the number of bit lines that can be programmed or read simultaneously is limited
Solution Approach 1:
The patent introduces bit line select gates as intermediary components between page buffers and bit lines. These select gates enable a page buffer to connect to multiple bit lines by sequentially enabling connections through the select gates. This intermediary mechanism allows one page buffer to effectively serve multiple bit lines, increasing simultaneous operations without complicating the direct page buffer-to-bit line connection architecture.
Data Source
AI summary
Methods and apparatus for memory operations disclosed. In an embodiment, a method is provided for programming multiple-level cells in a memory array. The memory array includes a plurality of planes and each plane includes a plurality of bit lines. The method includes storing multiple data bits in a first group of planes, one data bit per plane. The multiple data bits are stored in bit line capacitances of the first group of planes. The method also includes programming a selected multiple-level cell in a selected plane according to the multiple data bits that are stored in the bit line capacitances of the first group of planes. The selected plane is not one of the first group of planes.