NAND Flash Page Buffer Throughput via Bit Line Select Gates

The patent divides the memory array into multiple sub-arrays, with each sub-array having its own dedicated page buffer. This segmentation allows parallel access to multiple sub-arrays simultaneously, effectively increasing throughput without requiring a single large page buffer that would occupy excessive die area. Each sub-array can be independently accessed through its own page buffer, enabling concurrent operations.

The patent introduces bit line select gates that enable a single page buffer to connect to and control multiple bit lines across different sub-arrays. This adds a dimensional aspect to the page buffer connectivity, allowing one page buffer to serve multiple sub-arrays by selectively enabling connections to different bit lines, thereby increasing throughput without proportionally increasing page buffer area.

The patent makes page buffers multi-functional by enabling each page buffer to serve multiple sub-arrays through bit line select gates. A single page buffer can perform read and write operations on multiple sub-arrays by selectively activating connections to different bit lines, effectively increasing performance without requiring proportional increases in page buffer quantity or area.

The patent introduces dynamically controllable bit line select gates that can selectively connect page buffers to different bit lines and sub-arrays based on operational requirements. This dynamic connectivity allows the same hardware resources to be flexibly allocated to different sub-arrays, optimizing performance while maintaining efficient use of die area.