NAND Flash Memory Page-Dependent Verify Voltage Offset
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Solution Overview
Problem
In three-dimensionally stacked NAND flash memory devices, the threshold distribution of memory cells varies significantly due to program disturbance, leading to increased bit error rates and reduced operational reliability, especially as data is written across multiple pages.
Innovation Solution
The implementation of an offset table that adjusts the verify voltage based on page addresses and writing order, predicting and compensating for threshold shifts caused by program disturbance, thereby maintaining a desired threshold distribution across all pages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If data is written across multiple pages in three-dimensionally stacked NAND flash memory, then storage capacity is increased, but threshold distribution variation increases due to program disturbance
Solution Approach 1:
The patent applies preliminary action by predicting threshold shifts caused by program disturbance before they occur, and pre-adjusting verify voltages according to the writing order and page addresses. This allows the system to compensate for threshold distribution variations proactively, maintaining reliability while enabling multi-page data writing that increases storage capacity.
2Device complexity
If verify voltage is kept constant during multi-page writing, then device complexity is reduced, but bit error rate increases due to threshold shifts
Solution Approach 1:
The patent implements dynamics by making verify voltages adjustable and adaptive based on writing order and page addresses. Instead of using a fixed verify voltage, the system dynamically selects appropriate verify voltages from an offset table, allowing it to adapt to threshold shifts caused by program disturbance while maintaining manageable device complexity through systematic voltage selection.
3Manufacturing precision
If offset table adjusts verify voltage for each page, then threshold distribution accuracy is improved, but device complexity increases
Solution Approach 1:
The patent applies segmentation by organizing verify voltage adjustments into discrete offset values stored in an offset table, where each entry corresponds to specific writing scenarios. This segmented approach allows precise threshold distribution control through lookup-based voltage selection, managing complexity by breaking down the continuous adjustment problem into discrete, pre-calibrated steps.
Data Source
AI summary
A semiconductor memory device includes first to third pages, first to the third word lines, and a row decoder. In data writing, data is written into the first page before data is written into the second page. The row decoder is configured to apply first to third verify voltages to gates of first to third memory cells in a program verify operation.