NAND Flash Memory Parallel Access Architecture
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Solution Overview
Problem
NAND flash memory architectures face limitations in random access speed and efficiency due to their sequential access protocol, leading to slow data retrieval and programming, especially in compact designs where signal propagation times are increased, making them unsuitable for applications requiring fast code execution and boot operations without the use of a Program and Memory (PAM).
Innovation Solution
A modified NAND memory architecture with two submatrices, one for fast code storage and another for data storage, utilizing asynchronous and extended access protocols that allow direct and parallel addressing, reducing latency and increasing conductivity by sharing bit lines and row decoding circuitry, enabling faster random access and reducing the number of transistors in series.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional NAND memory architecture with sequential access protocol is used, then high density and low power consumption are achieved, but random access speed deteriorates
Solution Approach 1:
The memory matrix is divided into multiple submatrices, each accessible through independent bit line groups. This segmentation allows parallel access to different memory regions, enabling fast random access while maintaining the high-density NAND architecture. The row decoding circuitry is also segmented to handle different submatrices independently.
Solution Approach 2:
The patent introduces an additional addressing dimension by implementing both sequential (NAND-style) and direct (NOR-style) access protocols simultaneously. This allows the memory to operate in different access modes depending on the application requirements, achieving both high density and fast random access without compromising either.
2Quantity of substance
If lithographic sizes are reduced to increase memory density, then capacity increases, but signal propagation time increases due to longer lines
Solution Approach 1:
The memory is divided into multiple submatrices with independent bit line groups, reducing the physical length of signal lines within each submatrix. This segmentation maintains high memory capacity while reducing signal propagation delays by limiting the distance signals must travel within each memory block.
Solution Approach 2:
The patent introduces intermediate buffer circuits and level shifters between different memory submatrices and the control logic. These intermediaries reduce signal degradation and propagation delays by regenerating signals and optimizing voltage levels, enabling faster access across the entire high-capacity memory array.
3Area of stationary object
If row decoding circuitry is made compact to reduce area, then area occupation decreases, but access time increases due to complex decoding
Solution Approach 1:
The row decoding circuitry is segmented into multiple independent decoding units, each handling a specific submatrix. This allows parallel decoding operations to occur simultaneously in different segments, reducing the overall access time while keeping each decoding unit compact and area-efficient.
Solution Approach 2:
The patent implements pre-decoding logic that prepares address information in advance by splitting the address bus into multiple parts and pre-processing them in parallel. This preliminary action reduces the critical path delay during actual memory access, enabling faster read and write operations without increasing the area of the main decoding circuitry.
4Speed
If conventional NAND stack structure with 16-32 cells is used, then manufacturing is simplified, but reading speed deteriorates due to low conductivity
Solution Approach 1:
The patent implements different stack structures in different memory submatrices based on their specific access requirements. Some submatrices use conventional 16-32 cell stacks for high-density storage, while others use optimized stack structures with fewer cells in series for faster reading. This local optimization allows the memory system to achieve both high density and fast reading speeds simultaneously.
Solution Approach 2:
The patent introduces dynamically configurable stack structures where the number of cells in series can be adjusted based on the access mode. During sequential NAND-style operations, longer stacks are used for high density, while during random access operations, shorter stacks are activated for faster reading. This dynamic reconfiguration optimizes performance for different operational contexts.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances memory performance by achieving random access speeds comparable to NOR architectures, reducing circuit area, and eliminating the need for additional RAM for code execution, while maintaining compatibility with conventional NAND protocols, thus improving data storage and retrieval efficiency.
Implementation Method 1
The programming and erasing operations occur by exploiting the Fowler-Nordheim phenomenon
Data Source
AI summary
A method for accessing, in reading, programming, and erasing a semiconductor-integrated non-volatile memory device of the Flash EEPROM type with a NAND architecture having at least one memory matrix organized in rows or word lines and columns or bit lines, and wherein, for the memory, a plurality of additional address pins are provided. The method provides both an access protocol of the asynchronous type and a protocol of the extended type allowing to address, directly and in parallel, a memory extended portion by loading an address register associated with the additional pins in two successive clock pulses. A third multi-sequential access mode and a parallel additional bus referring to the additional address pins are also provided to allow a double addressing mode, sequential and in parallel.