NAND Flash Memory Parallel Precharge and Latch Initialization
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Solution Overview
Problem
Conventional NAND flash memory reading methods are slow due to sequential initialization and precharging of bit lines, which prolongs the reading time and affects data retention characteristics.
Innovation Solution
A high-speed reading method that initializes the latch and page buffer/reading circuit in parallel with precharging the selected bit line, using a dual voltage supply system to precharge the selected bit line and shield the non-selected bit line, thereby reducing noise and shortening the overall reading time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sequential initialization and precharging of bit lines is performed, then the reading operation can be completed with proper signal preparation, but the reading time becomes prolonged (7-8 μs)
Solution Approach 1:
The patent applies preliminary action by precharging the selected bit line before the reading operation begins, and by initializing the latch in parallel with this precharging step rather than sequentially. This prepares the necessary conditions in advance, allowing the actual reading to start immediately without waiting for sequential completion of initialization steps.
Solution Approach 2:
The patent achieves continuity of useful action by overlapping the latch initialization process with the bit line precharging process. Both operations occur simultaneously rather than one after another, maximizing the utilization of the reading circuit's capabilities and eliminating idle time between operations.
2Loss of time
If parallel initialization and precharging operations are performed, then the reading time is significantly reduced (2-3 μs), but the circuit complexity increases due to dual voltage supply coordination
Solution Approach 1:
The patent applies universality by using a dual voltage supply system where one voltage supply (first voltage supply) is responsible for precharging the selected bit line, and another voltage supply (second voltage supply) initializes the latch. These multi-functional voltage supplies coordinate to perform multiple operations in parallel, reducing overall reading time despite increased circuit complexity.
Data Source
AI summary
The disclosure provides a semiconductor device and a reading method capable of achieving high-speed reading performance. A NAND flash memory according to the disclosure includes: a bit line selection circuit for selecting an even-numbered bit line or an odd-numbered bit line, and a page buffer/reading circuit connected to the bit line selection circuit. A reading method of a flash memory includes: precharging the selected bit line with a virtual power supply (VIRPWR) connected to the bit line selection circuit (step #1); and initializing a latch circuit (L1) through a voltage supply node V1 in parallel with the precharging of the selected bit line (step #1_2); and initializing the page buffer/reading circuit 170 through the voltage supply node V1 (step #1_3).