NAND Flash Memory Read Architecture for Parallel String Access
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Solution Overview
Problem
Existing memory systems face challenges in speeding up read operations in NAND-type flash memory devices.
Innovation Solution
The memory system employs a configuration with first and second strings connected to bit lines and gate lines, allowing for independent control of memory cells during read operations, applying specific voltages to turn on or off transistors based on charge states, thereby optimizing read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional read operations are used in NAND-type flash memory, then the read operation can be completed, but the read operation speed is slow
Solution Approach 1:
The memory array is divided into multiple independent string units (first string with first and second memory cells, third string with third and fourth memory cells), each capable of being read independently. This segmentation allows parallel read operations on different strings, significantly increasing read speed and reducing the time required to complete read operations.
Solution Approach 2:
Multiple memory cells (first memory cell, second memory cell, third memory cell, fourth memory cell) are combined into a single read operation through shared bit lines and word lines. The circuit configuration allows simultaneous reading of multiple cells by applying appropriate voltages to gate lines and bit lines, thereby increasing throughput without proportionally increasing operation time.
2Productivity
If multiple memory cells are read simultaneously, then read operation speed increases, but interference between memory cells occurs
Solution Approach 1:
Different voltage levels are applied to different gate lines to create distinct electrical environments for each memory cell being read. The first gate line receives a first voltage while the second gate line receives a second voltage, allowing selective activation of specific transistors and isolation of adjacent memory cells, thus preventing interference while enabling parallel reads.
Solution Approach 2:
The patent utilizes different voltage parameters (first voltage, second voltage, third voltage, fourth voltage) applied to different gate lines and bit lines to control the state of transistors and memory cells. By dynamically changing voltage parameters during the read operation, the system can selectively turn on/off specific cells, enabling parallel reads without interference and maintaining high reliability.
Data Source
AI summary
A memory system for speeding up a read operation in the memory system includes a first pillar, a first string including a first transistor and a first memory cell, a second string including a second transistor and a second memory cell, a first bit line, a first gate line, a first word line, a second gate line, a second word line and a control circuit. When the control circuit executes a read operation with respect to the first memory cell, the control circuit is configured to apply a read voltage to the first word line, apply a voltage turning off the second memory cell regardless of an electric charge stored in the second memory cell to the second word line, apply a voltage turning on the first transistor to the first gate line, and apply a voltage turning on the second transistor to the second gate line.