NAND Flash Memory Structure Reducing Parasitic Capacitance
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Solution Overview
Problem
As memory cell sizes decrease, the distance between floating gates in NAND flash memory devices becomes shorter, leading to increased parasitic capacitance and cell interference due to adjacent floating gates facing each other, which affects the read and write operations.
Innovation Solution
The nonvolatile memory structure and manufacturing method involve creating a larger electrical coupling distance between charge storage patterns by using upper and lower control gates with specific width and gradient configurations, where the lower control gates protrude or are recessed to prevent adjacent charge storage patterns from facing each other, thereby reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell sizes are reduced to increase storage capacity, then storage density is improved, but parasitic capacitance between adjacent floating gates increases due to shorter distances
Solution Approach 1:
The patent introduces a third vertical dimension by stacking control gates above and below the charge storage layer. This vertical arrangement allows the control gates to influence charge storage patterns without increasing lateral parasitic capacitance between adjacent floating gates, thus maintaining high storage density while reducing harmful electromagnetic coupling.
Solution Approach 2:
The patent introduces blocking insulation layers as intermediary elements between adjacent charge storage patterns. These blocking layers act as electromagnetic shields that prevent direct capacitive coupling between neighboring floating gates, thereby reducing parasitic capacitance while allowing the memory cells to remain closely spaced for high density.
2Quantity of substance
If distance between adjacent charge storage patterns is reduced to increase storage capacity, then storage density is improved, but cell interference increases due to floating gates facing each other
Solution Approach 1:
By moving control gates to vertical positions above and below the charge storage layer, the patent creates a three-dimensional control structure. This allows adjacent charge storage patterns to be positioned closer together laterally without direct facing of control gate surfaces, reducing capacitive interference while maintaining high storage density through vertical space utilization.
Solution Approach 2:
Blocking insulation layers are positioned between adjacent charge storage patterns to serve as intermediary barriers. These layers prevent direct electromagnetic interaction between neighboring cells, reducing cell interference and improving reliability while allowing tighter spacing for increased storage capacity.
3Device complexity
If control gates are positioned directly above charge storage patterns to simplify structure, then manufacturing complexity is reduced, but parasitic capacitance increases due to shorter electrical coupling distance
Solution Approach 1:
The patent positions control gates in the vertical dimension above and below the charge storage layer rather than directly adjacent in the lateral plane. This vertical separation increases the electrical coupling distance between control gates and charge storage patterns, reducing parasitic capacitance while maintaining a relatively simple stacked structure that can be manufactured using standard semiconductor processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively minimizes parasitic capacitance, reducing cell interference and improving the operational efficiency of NAND flash memory devices by maintaining a larger coupling distance between charge storage patterns compared to their direct geometric distance.
Implementation Method 1
a high electric field may be generated between a floating gate and a channel region
Implementation Method 2
As charge moves through the tunneling oxide in one direction or the other, the threshold voltage (Vth) of the memory cell is changed
Implementation Method 3
the distance between floating gates 32 becomes shorter. The shorter the distance of the floating gates 32 becomes, the larger parasitic capacitances (C) become
Data Source
AI summary
Example embodiments are directed to a method of forming a nonvolatile memory structure and a nonvolatile memory structure including a plurality of charge storage patterns, wherein an electrical coupling distance (Lc) between adjacent charge storage patterns is larger than a direct geometric distance (Ls) between adjacent charge storage patterns.