NAND Flash Parity Grouping for Pillar-Failure Fault Tolerance

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Solution Overview

Problem

Existing 2WL RAIN protection in NAND flash memory systems is susceptible to pillar-related failures while maintaining storage efficiency, which current redundancy mechanisms fail to adequately address.

Innovation Solution

Organizing pages from a block into separate RAIN parity groups by calculating parity group identifiers using specific equations based on block type, performing XOR operations to generate redundancy metadata, and reconstructing defective pages using stored metadata.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional 2WL RAIN protection is used, then storage efficiency is maintained, but the system is susceptible to pillar-related failures

Engineering Contradiction:
Improveprotection against pillar-related failuresVSAvoidredundancy mechanism complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent divides the block into multiple parity groups (first parity group and second parity group) with different protection levels. The first parity group provides standard 2WL RAIN protection while the second parity group provides enhanced protection against pillar-related failures. This segmentation allows the system to protect against pillar failures without applying complex redundancy to the entire block, thus maintaining storage efficiency while improving reliability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies different redundancy strategies to different regions (parity groups) within the block based on their specific protection needs. Pages in the first parity group use standard 2WL RAIN protection, while pages in the second parity group use enhanced protection mechanisms. This local differentiation allows the system to address pillar-related failures in specific areas without unnecessarily complicating the entire storage structure.

Inventive Principle:
Principle #3Local quality

2Reliability

If enhanced redundancy mechanisms are implemented, then protection against pillar-related failures improves, but storage efficiency decreases

Engineering Contradiction:
Improvefault toleranceVSAvoidstorage capacity
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

By segmenting the block into multiple parity groups with different protection levels, the patent ensures that enhanced redundancy is applied only where necessary (second parity group for pillar failure protection) rather than across the entire block. This selective approach maintains overall storage capacity while providing targeted fault tolerance against pillar-related failures.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements enhanced protection partially - only for the second parity group that is vulnerable to pillar-related failures, rather than applying excessive redundancy to all data. This partial action provides sufficient fault tolerance for the specific threat while minimizing the impact on storage efficiency.

Inventive Principle:
Principle #16Partial or excessive action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enhances protection against wordline-level failures and pillar-related defects in NAND flash memory systems without reducing storage efficiency, providing robust fault tolerance.

Implementation Method 1

performing XOR operations to generate redundancy metadata

Methodology Applied
Scientific EffectXOR operation:

Data Source

PatentUS20250370633A1Enhanced parity formation for fault tolerance in memory devices
Publication Date: 2025.12.04 MICRON TECHNOLOGY INC
  • US20250370633A1 patent drawing
  • US20250370633A1 patent drawing
  • US20250370633A1 patent drawing

AI summary

A parity group identifier is calculated for each page of a plurality of pages of a block of a memory device storing host data based on a page number of a respective page and a wordline number derived from the page number. The page number is appended to an array of page numbers assigned to a parity group identified by the parity group identifier. Redundancy metadata is calculated for each parity group of a plurality of parity groups based on the array of page numbers assigned to a respective parity group. The redundancy metadata is stored in a page of the block identified by a last page number of the array of page numbers assigned to the respective parity group.