NAND Flash Block Verification Using Partial String Sampling

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Solution Overview

Problem

NAND flash memory with single-level cells (SLCs) requires a long program time due to the one-program-one-verification (1P1V) method, which affects program speed.

Innovation Solution

Reduce program time by verifying less than all memory strings in a memory block after programming, using a reduced number of verification pulses, and determining successful programming based on the verification of selected memory strings.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the one-program-one-verification (1P1V) method is used to program NAND flash memory, then programming reliability is improved, but program time increases

Engineering Contradiction:

Improveprogramming reliabilityVSAvoidprogram time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent applies partial verification by selecting only certain memory strings for verification after programming, rather than verifying all memory strings. This partial action reduces the total verification time while maintaining acceptable programming reliability through sampling-based quality assurance

Inventive Principle:

Principle #16Partial or excessive action

Solution Approach 2:

The patent segments the verification process by dividing memory strings into different groups (first set and second set) with different verification strategies. The first set undergoes traditional verification while the second set uses reduced verification, allowing the system to balance reliability and speed for different memory regions

Inventive Principle:

Principle #1Segmentation

2Manufacturing precision

If verification pulses are applied to all memory strings, then programming accuracy is improved, but program speed decreases

Engineering Contradiction:

Improveprogramming accuracyVSAvoidprogram speed

Core Design Contradiction:

Manufacturing precisionVSProductivity

Solution Approach 1:

The patent implements partial verification by applying verification pulses to only a subset of memory strings (first set) rather than all memory strings. This partial action maintains programming accuracy for critical regions while improving overall program speed through selective verification

Inventive Principle:

Principle #16Partial or excessive action

Solution Approach 2:

The patent applies different verification quality levels to different memory string groups. The first set of memory strings receives full verification for high accuracy, while the second set receives reduced verification, creating local quality differentiation that balances overall system performance

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS20260011381A1Methods and apparatuses for operating a memory device

Publication Date: 2026.01.08 YANGTZE MEMORY TECH CO LTD

AI summary

Methods, devices, and systems for managing memory devices are provided. In one aspect, a method for operating a memory device includes programming a memory block of the memory device by programming each of a set of memory strings included in the memory block, and verifying the memory block by verifying less than all the set of memory strings in the memory block.