NAND Flash Memory Peripheral Structure Area Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional three-dimensional NAND type flash memory devices face increased chip area due to the stepped wiring line portion, which expands as the number of memory layers increases, leading to a larger peripheral circuit and overall memory chip area.
Innovation Solution
The design includes a memory cell array with stacked conductive layers connected to memory cells, where the wiring line portion features second conductive layers with ends positioned differently in a crossing direction, a channel semiconductor layer, and a gate electrode layer on a gate insulating film, allowing the word line and bit line connection circuits to be disposed overlapping the stepped wiring line portion, thereby reducing the chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the stacking number of memory layers is increased to achieve higher integration, then the memory capacity is improved, but the area of the stepped wiring line portion increases, leading to larger chip area
Solution Approach 1:
The patent transitions from a planar wiring layout to a three-dimensional stacked architecture where word lines are formed in multiple layers (first through fourth word lines) extending in the vertical stacking direction. This dimensional change allows the wiring connections to occupy the vertical space rather than spreading horizontally, thereby maintaining memory capacity while reducing the footprint area of the stepped wiring line portion.
Solution Approach 2:
The patent implements a nested structure where multiple word line layers are stacked vertically within the same horizontal footprint. The first, second, third, and fourth word lines are arranged in overlapping vertical positions, with each layer nested within the overall memory block structure. This nesting allows efficient use of vertical space to accommodate increased memory capacity without proportionally increasing chip area.
2Quantity of substance
If the stacking number of memory layers is increased, then the memory capacity is improved, but the peripheral circuit area increases, leading to larger chip area
Solution Approach 1:
The patent merges the peripheral circuit functions into the same vertical columnar structure as the memory cells. The bit line connection circuit and word line connection circuit are integrated within the memory block, sharing the same vertical space and structural elements (such as the stacked word lines and contact plugs). This merging eliminates the need for separate peripheral circuit areas, allowing peripheral circuit functionality to be achieved within the existing memory array footprint.
3Ease of operation
If conventional stepped wiring line structure is used, then connection to peripheral circuits is achieved, but the wiring line area ends up increasing with stacking number
Solution Approach 1:
The patent segments the wiring line into multiple discrete conductive layers (first word line, second word line, third word line, fourth word line) stacked vertically. Each word line layer is a separate conductive structure that can be independently formed and connected. This segmentation allows the total wiring function to be distributed across multiple small vertical segments rather than requiring a large continuous horizontal wiring area, thereby reducing the overall wiring line area while maintaining connection capability.
Data Source
AI summary
This nonvolatile semiconductor memory device comprises: a memory cell array including memory cells; and a wiring line portion connecting the memory cell array to an external circuit. The memory cell array comprises a plurality of first conductive layers which are connected to the memory cells and arranged in a stacking direction. On the other hand, the wiring line portion comprises: a plurality of second conductive layers arranged in the stacking direction and respectively connected to the plurality of first conductive layers, positions of ends of the plurality of second conductive layers being different in a first direction crossing the stacking direction; a third conductive layer extending in the stacking direction from the second conductive layer; a channel semiconductor layer connected to one end of the third conductive layer; and a gate electrode wiring line disposed on a surface of the channel semiconductor layer via a gate insulating film.