NAND Flash Memory Pillar Penetration and Gate Formation
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Solution Overview
Problem
Current NAND-type flash memory devices face challenges in increasing storage capacity per unit area while maintaining consistent transistor characteristics and reducing manufacturing complexity and costs.
Innovation Solution
The semiconductor memory device employs a configuration where memory pillars penetrate stacked word lines, allowing overlap between slits and memory pillars, and uses a doped semiconductor layer as a gate electrode, which is formed after slit formation, ensuring uniformity and reducing variations in transistor characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If memory pillars are formed before slits, then manufacturing process is simpler, but transistor characteristics show large variations
Solution Approach 1:
The patent applies preliminary action by forming the slits in the insulating film before forming the memory pillars. This reverses the conventional sequence and allows the memory pillars to be formed with precise positioning relative to the pre-formed slits, ensuring uniform transistor characteristics while maintaining a relatively simple manufacturing process.
2Quantity of substance
If storage capacity per unit area is increased, then device functionality is improved, but transistor characteristic variations increase
Solution Approach 1:
The patent increases storage capacity by forming memory pillars in a staggered arrangement across multiple levels, utilizing vertical and diagonal dimensions. This multi-dimensional approach allows higher density while maintaining uniform transistor characteristics through precise control of pillar positions relative to the insulating film structure.
3Ease of manufacture
If doped semiconductor layer is formed before slits, then process sequence is conventional, but gate electrode uniformity is poor
Solution Approach 1:
The patent forms the slits in the insulating film before forming the doped semiconductor layer that serves as the gate electrode. This preliminary action ensures that the gate electrode is formed with uniform thickness and doping characteristics, as the pre-formed slits provide a consistent template for subsequent material deposition and processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances storage capacity per unit area, reduces transistor variation, and simplifies the manufacturing process, thereby improving yield and reducing costs.
Implementation Method 1
uses a doped semiconductor layer as a gate electrode, which is formed after slit formation
Data Source
AI summary
A semiconductor device according to an embodiment includes first conductors, a second conductor, a first semiconductor, a multi-layered body, and a third conductor. The second conductor is provided above the first conductors. The multi-layered body is provided between the first semiconductor and the first conductors, and between the first semiconductor and the second conductor. The third conductor is provided between the multi-layered body and the second conductor. The first semiconductor includes a first portion facing an uppermost first conductor and a second portion facing the second conductor. The first semiconductor is continuous at least from the first portion to the second portion.