NAND Flash Memory Plug Formation via Segmented Insulating Layers
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Solution Overview
Problem
Conventional manufacturing techniques are not well-suited for forming the precise dimensions required in next-generation NAND type flash memory devices, leading to potential electrical shorts and inadequate exposure of underlying features due to imprecise processing conditions.
Innovation Solution
A method of forming a NAND type flash memory device that includes forming device isolation layers, common source and drain regions, and insulating layers to define active regions, with specific patterning and plug structures to ensure precise connection and exposure of regions, allowing for the formation of bit lines and plugs that reduce contact resistance and enhance integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional manufacturing techniques are used to form openings in NAND type flash memory devices, then the processing steps are simpler and easier to implement, but the precision of opening formation deteriorates leading to electrical shorts and inadequate exposure of underlying features
Solution Approach 1:
The patent divides the formation of openings into multiple sequential steps: first forming contact holes through the first interlayer insulating layer, then forming via holes through both insulating layers. This segmentation allows each step to be optimized independently for precision while managing overall process complexity.
Solution Approach 2:
The patent performs preliminary actions by forming the first interlayer insulating layer and contact holes before forming the second interlayer insulating layer and via holes. This preliminary structuring establishes precise reference points and protective layers that enable subsequent high-precision opening formation.
2Reliability
If the degree of integration in NAND type flash memory devices is increased, then the storage capacity and performance improve, but the line widths decrease and opening depths increase making conventional techniques inadequate
Solution Approach 1:
The patent addresses the increased opening depth by introducing a vertical layering dimension with multiple insulating layers (first and second interlayer insulating layers) and corresponding openings at different depths (contact holes and via holes). This dimensional approach allows precise control of each opening's depth and position to accommodate higher integration requirements.
Solution Approach 2:
The patent implements a nested structure where the second interlayer insulating layer is formed over the first interlayer insulating layer, and via holes penetrate both layers to reach underlying contact holes. This nested arrangement of insulating layers and interconnected openings enables precise dimensional control for highly integrated devices.
3Reliability
If openings are formed wider than desired to ensure exposure of underlying features, then the exposure reliability improves, but electrical shorts may occur between adjacent structures
Solution Approach 1:
The patent applies different opening dimensions at different locations: contact holes have a first width, while via holes have a second width that is narrower. This local differentiation allows each opening type to be optimized for its specific function - contact holes provide adequate exposure while via holes maintain narrow dimensions to prevent shorts between adjacent bit lines.
Solution Approach 2:
Instead of forming one wide opening that risks creating shorts, the patent inverts the approach by forming multiple narrower openings (contact holes and via holes) at different levels and positions. This inverted strategy achieves reliable feature exposure through the cumulative effect of multiple precisely positioned narrow openings rather than a single wide opening.
Data Source
AI summary
In a NAND type nonvolatile memory device, a first insulating layer covers a common drain region formed in a string active region and a peripheral active region. A second insulating layer covers the first insulating layer. A bit line plug penetrates the first and second insulating layers and is connected to the common drain region. A peripheral lower plug penetrates the first insulating layer and is connected to the peripheral active region. A peripheral upper plug penetrates the second insulating layer and is stacked on the peripheral lower plug.