NAND Flash Pre-Erase Control for Adaptive Write Workloads

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Solution Overview

Problem

Existing pre-erase strategies in NAND-type flash memory are inflexible and do not adapt to changes in write operations, leading to stability risks and inefficiencies due to fixed pre-erase volume thresholds and uncontrolled pre-erased blocks.

Innovation Solution

A memory management method that dynamically adjusts pre-erase modes based on the actual data writing situation, allowing for adaptive control between automatic and active modes to optimize pre-erase operations according to application scenarios and application programs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a pre-erase operation is performed on a new block before writing data, then write reliability is improved, but write speed deteriorates due to the additional erase step

Engineering Contradiction:
Improvewrite reliabilityVSAvoidwrite speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The system performs pre-erase operations in advance during idle periods or when switching blocks, preparing erased blocks before they are needed for writing. This separates the erase preparation from the critical write path, maintaining write speed while ensuring reliability when data needs to be written.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements dynamic pre-erase mode switching between automatic and active modes based on system conditions. The automatic mode enables background pre-erase operations that don't interfere with write speed, while the active mode provides on-demand pre-erase when reliability is prioritized, allowing the system to adapt to different operational requirements.

Inventive Principle:
Principle #15Dynamics

2Device complexity

If a fixed pre-erase volume threshold is used, then device complexity is reduced, but adaptability to different write scenarios deteriorates

Engineering Contradiction:
Improvecontrol complexityVSAvoidadaptability to write scenarios
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The system dynamically adjusts pre-erase thresholds and mode selection based on actual write patterns, workload characteristics, and system state. Instead of fixed thresholds, the controller adapts pre-erase parameters to match different write scenarios, improving versatility while maintaining manageable complexity through automated adaptation.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes pre-erase operation parameters (such as threshold values, mode selection, and timing) based on detected write scenarios and system conditions. This allows the system to optimize pre-erase behavior for different workloads without requiring complex manual configuration or fixed rigid controls.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If pre-erase operations are performed frequently to ensure availability of erased blocks, then write availability is improved, but energy consumption increases

Engineering Contradiction:
Improvewrite availabilityVSAvoidenergy consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The system performs pre-erase operations periodically during idle periods or scheduled maintenance windows rather than continuously or on every write operation. This timing strategy ensures erased blocks are available when needed while concentrating energy consumption in non-critical periods, reducing overall energy impact on write operations.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The patent implements dynamic control of pre-erase frequency based on system state, write queue depth, and power management requirements. When power saving is prioritized, pre-erase operations are reduced or deferred; when write availability is critical, pre-erase frequency increases. This dynamic adjustment balances energy consumption against write availability based on current system needs.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentEP4722885A1Memory management method and apparatus, and storage system and computer-readable medium
Publication Date: 2026.04.08 GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP LTD
  • EP4722885A1 patent drawingFigure 1~3
  • EP4722885A1 patent drawingFigure 4~5
  • EP4722885A1 patent drawingFigure 6~7

AI summary

A memory management method, and a storage system (10) are provided. The method may include: determining (S201) a target pre-erasing mode among an automatic mode and an active mode, wherein in the automatic mode, the memory automatically performs a pre-erase operation on the memory (200), and in the active mode, the memory (200) performs the pre-erase operation according to an instruction sent by a host (100); and performing (S202) the pre-erase operation on the memory (200) based on the target pre-erase mode.