NAND Flash Controller Priority Decoding Queues
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Solution Overview
Problem
Multi-level cell (MLC) NAND Flash memory experiences a higher raw bit error rate than single-level cell (SLC) NAND Flash memory, requiring more advanced error correction schemes that increase data access latency, necessitating a method to differentiate memory access operations based on priority to optimize performance.
Innovation Solution
Implementing a NAND Flash memory controller with separate task queues for decoding tasks of different priorities, utilizing multiple decoders with varying error-correcting code schemes, and input switching circuitry to direct data to appropriate decoders based on priority, allowing for prioritization of decoding tasks and efficient data handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If advanced error correction schemes are used in MLC NAND Flash memory, then reliability is improved, but data access latency increases
Solution Approach 1:
The patent segments decoding tasks into multiple priority levels (first priority, second priority, etc.) and processes them through separate queues. High-priority tasks that are latency-sensitive use simpler decoding schemes, while lower-priority tasks use more comprehensive error correction, thus resolving the contradiction between reliability and latency by differentiating treatment based on task urgency
Solution Approach 2:
Different decoding schemes are applied to different tasks based on their specific requirements. The system applies simple decoding to high-priority tasks requiring low latency, and advanced error correction to lower-priority tasks where reliability is more critical, achieving local optimization of the reliability-latency tradeoff
2Reliability
If advanced error correction schemes are used, then reliability is improved, but decoding complexity increases
Solution Approach 1:
The patent divides the decoding workload into multiple priority-based queues, allowing the system to use simple decoding logic for high-priority tasks and reserve complex error correction resources for lower-priority tasks. This segmentation reduces the average decoding complexity experienced by the system while maintaining high reliability where needed
Solution Approach 2:
The system dynamically changes the decoding parameter (complexity level) based on task priority. High-priority tasks are decoded with simpler parameters (faster, lower complexity), while lower-priority tasks use more complex parameters (slower, higher complexity but more reliable), optimizing the balance between reliability and complexity
3Productivity
If simpler decoding schemes are used for most operations, then throughput is improved, but latency for critical operations increases
Solution Approach 1:
The patent implements separate priority queues that segment the task stream, allowing the majority of operations to be processed through simple decoding paths (maintaining high throughput) while providing a dedicated fast path for critical high-priority operations (maintaining low latency when needed), thus resolving the throughput-latency tradeoff
Solution Approach 2:
The system performs preliminary classification of tasks into priority levels before decoding. High-priority tasks are identified and routed to appropriate decoding paths in advance, ensuring they receive timely processing without blocking the overall throughput of lower-priority operations
Data Source
AI summary
Apparatus, for performing decoding tasks in a NAND Flash memory controller, includes a first task queue for queuing decoding tasks of a first priority, a second task queue for queuing decoding tasks of a second priority higher than the first priority, and control circuitry that, on receipt of portions of data for a plurality of decoding tasks, releases, from the first and second task queues, respective decoding tasks to operate on respective portions of data, according to priorities of the decoding tasks. First and second decoders operate under first and second decoding schemes that differ in speed or complexity. Input switching circuitry controllably connects each data channel to the first or second decoder. Decoder-done control circuitry selects output of the first or second decoder upon receipt of a decoder-done signal from the first or second decoder. Completed decoding tasks are queued in first and second task-done queues according to priority.