Automatic Read Calibration for NAND Flash Memory
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Solution Overview
Problem
Conventional automatic read calibration methods in computer systems, particularly in memory devices like NAND flash, are inefficient in terms of performance impact and compatibility with program suspend operations, and fail to optimize bit error rate in corner cases such as centered or extreme read voltage levels.
Innovation Solution
The implementation of segmented and fast automatic read calibration methods, which reduce performance impact by calculating optimal read voltage levels through interpolated histograms and calibrated parameters, enabling earlier calibration and compatibility with program suspend operations, thus improving bit error rate and quality of service.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional automatic read calibration methods are used, then bit error rate is optimized, but performance impact increases significantly (10× slowdown)
Solution Approach 1:
The patent divides the read calibration process into multiple segments or phases. Instead of performing a complete calibration sequence for every read operation, the system segments the calibration into initial calibration, periodic recalibration, and on-demand calibration components. This segmentation reduces the average performance impact while maintaining bit error rate optimization through selective calibration execution.
Solution Approach 2:
The patent implements preliminary calibration actions by pre-calibrating read voltage levels during manufacturing or initial system setup, and by performing calibration predictions based on historical data and workload patterns. This preliminary action allows the system to avoid full calibration sequences during normal operations, reducing performance impact while maintaining reliability.
2Reliability
If conventional automatic read calibration methods are used, then bit error rate is optimized, but compatibility with program suspend operations is lost
Solution Approach 1:
The patent introduces dynamic calibration strategies that adapt to the operational state of the system. When program suspend operations are detected or anticipated, the calibration process is dynamically adjusted or postponed. The system monitors operation types and dynamically selects appropriate calibration timing, ensuring compatibility with program suspend while maintaining bit error rate optimization through calibration at appropriate moments.
Solution Approach 2:
The patent changes calibration parameters such as calibration frequency, voltage level adjustment steps, and histogram analysis thresholds based on operational context. When program suspend operations are active, calibration parameters are modified to reduce interference or timing conflicts, thereby maintaining compatibility while preserving bit error rate performance through context-aware parameter adjustment.
3Measurement precision
If conventional automatic read calibration methods are used, then calibration accuracy is achieved, but performance impact increases and corner cases are not handled optimally
Solution Approach 1:
The patent applies local quality by performing high-precision calibration only in specific contexts or for specific data regions that require it. Instead of uniform high-precision calibration across all operations, the system identifies corner cases and applies enhanced calibration accuracy locally where needed, while using faster, lower-precision methods for routine operations. This maintains measurement precision for critical cases while reducing overall performance impact.
Solution Approach 2:
The patent implements partial calibration actions by performing histogram analysis and voltage adjustment only for the specific read levels or data pages that require calibration, rather than comprehensive calibration of all parameters. This partial action approach achieves sufficient calibration accuracy for corner cases while avoiding the excessive performance cost of complete calibration sequences.
Data Source
AI summary
An apparatus comprises a plurality of memory cells; a plurality of sense circuits, a sense circuit comprising a sense node selectively coupled to a bitline coupled to a first cell of the plurality of memory cells; and a controller to transpose a value indicative of a voltage of the first cell to the sense node; isolate the sense node from the bitline; and calibrate a parameter for the sense circuit based on outputs of the sense circuit for each of a plurality of different applied values of the parameter.