NAND Flash Read Circuit with Constant Bit Line Discharge
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Solution Overview
Problem
NAND flash memory devices with multiple voltage threshold levels face significant increases in read and program time due to the need to check and verify multiple voltage levels, leading to longer latency and reduced throughput.
Innovation Solution
A method and apparatus that utilize constant bit line discharging speed by precharging bit lines and applying a sequence of word line voltages, controlling the discharging current to achieve identical discharge rates across multiple bit lines, allowing for simultaneous discharge and data latching in a single cycle, thereby reducing read and program-verify time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple voltage threshold levels are used to increase memory capacity, then storage density is improved, but read time and program time are significantly increased
Solution Approach 1:
The patent applies preliminary action by precharging all bit lines to a reference voltage level before the read operation begins. This preparation step ensures that when multiple voltage threshold levels need to be read, the bit lines are already in the correct initial state, allowing for faster subsequent operations without requiring sequential charging for each voltage level check.
Solution Approach 2:
The patent implements continuity of useful action by conducting all voltage threshold level readings simultaneously in a single discharge cycle. Instead of sequentially checking each voltage level (which would require multiple separate operations), the system continuously monitors multiple thresholds at once through parallel bit line discharges, eliminating idle time between measurements.
2Quantity of substance
If multiple voltage threshold levels are used to increase memory capacity, then storage density is improved, but program-verify time is significantly increased
Solution Approach 1:
The patent merges multiple verify operations into a single integrated process. By combining all voltage threshold level verifications into one simultaneous discharge cycle, the system eliminates the need for separate verify steps for each threshold level, thereby reducing the overall program-verify time while maintaining accurate verification of all stored data levels.
Solution Approach 2:
The patent applies preliminary action by precharging bit lines before the program-verify operation. This ensures that when program verification needs to check multiple voltage thresholds, the bit lines are already prepared in the correct initial state, allowing for faster simultaneous verification of all programmed data without sequential delays.
3Measurement precision
If sequential reading of multiple voltage levels is performed, then data accuracy is maintained, but read latency is increased
Solution Approach 1:
The patent transitions from sequential (one-dimensional) reading to parallel (multi-dimensional) reading by utilizing multiple bit lines that can discharge simultaneously. Each bit line independently monitors a specific voltage threshold level, allowing the system to read multiple data levels at the same time rather than one after another, thereby maintaining accuracy while dramatically reducing latency.
Solution Approach 2:
The patent segments the read operation by assigning different bit lines to monitor different voltage threshold levels. This segmentation allows each bit line to independently and simultaneously detect its assigned threshold, enabling parallel processing of multiple data levels while maintaining the precision of individual threshold detection through dedicated detection paths.
Data Source
AI summary
Methods and apparatus for reading NAND flash memory are disclosed. In an embodiment, a method is provided for reading a NAND flash memory that includes strings of memory cells that are coupled to bit lines and word lines. The method includes precharging a plurality of bit lines to a precharge voltage level, and applying a sequence of word line voltages to a selected word line. The method also includes initiating discharge of one or more bit lines associated with one or more cells, respectively. The method also includes controlling discharging current of discharging bit lines to achieve identical discharge rates, waiting for a discharging time period for each bit line that is discharging, and latching bit line data at an end of each discharge time period.