NAND Flash Memory Read Disturb Mitigation via Access Counting
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Solution Overview
Problem
The reliability of data stored in NAND flash memory is compromised due to read disturb phenomena, where frequent read operations degrade the erase state of memory cells, leading to increased bit error ratios and reduced data integrity.
Innovation Solution
A memory system with an access counter circuit that counts read accesses to determine when refresh operations are necessary, incrementing a counter value for blocks identified as open to manage and recover data reliability by executing refresh operations before significant degradation occurs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If read operations are performed frequently to access data in NAND flash memory, then data accessibility is improved, but read disturb effects degrade the erase state of memory cells leading to increased bit error ratios
Solution Approach 1:
The patent performs preliminary actions by counting read accesses before significant degradation occurs. The access counter circuit monitors read operations and triggers refresh operations proactively when a threshold is reached, preventing read disturb effects from degrading data integrity rather than correcting errors after they occur.
Solution Approach 2:
The patent implements feedback by using the access counter circuit to monitor read access frequency and provide this information to the refresh control logic. This feedback mechanism enables the system to adjust refresh timing based on actual read patterns, triggering refresh operations when necessary to maintain data integrity while avoiding unnecessary refreshes that would waste power.
2Reliability
If refresh operations are performed frequently to maintain data reliability, then bit error ratios are reduced, but power consumption increases
Solution Approach 1:
The system performs refresh operations preliminarily when the read access count reaches a threshold, before significant degradation occurs. This proactive approach maintains data reliability while avoiding continuous or overly frequent refresh operations that would unnecessarily consume power.
Solution Approach 2:
The patent implements periodic refresh operations based on read access counting. Instead of continuous refreshing, the system periodically triggers refresh operations at intervals determined by the read access threshold, reducing overall power consumption while maintaining adequate data reliability.
3Reliability
If access counting and refresh management circuits are added to track read accesses, then data reliability is maintained, but device complexity increases
Solution Approach 1:
The patent segments the memory system into distinct functional components: the access counter circuit that tracks read accesses, the threshold comparison logic, and the refresh control circuit. This segmentation allows each component to perform its specific function efficiently, managing overall system complexity through modular design.
Solution Approach 2:
The access counter circuit serves multiple functions: it counts read accesses, compares the count against a threshold, and triggers refresh operations when necessary. This multi-functionality reduces the need for separate dedicated circuits for each task, thereby managing device complexity while maintaining data reliability.
Data Source
AI summary
According to one embodiment, a non-volatile first memory includes a plurality of first storage areas. A second memory stores a plurality of first addresses each is address information of a second storage area. The second storage area is a first storage area in a first state. A third memory stores a counted value for the second storage area. A determiner circuit reads, at a time of a read access to the first memory, at least one of the first addresses and compares the read second address with a third address to determine whether a third storage area is in the first state. The third address indicates a location of the third storage area. The third storage area is a first storage area to be read. An update circuit increments, for the third storage area, the counted value, when the third storage area is in the first state.