NAND Flash Read Disturbance Mitigation via Localized Pass Voltage
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Solution Overview
Problem
Flash memory devices, particularly NAND flash memory devices, experience read disturbances due to hot carriers causing threshold voltage abnormalities, leading to incorrect state readings during repetitive read operations.
Innovation Solution
A method of reading NAND flash memory devices involves applying specific voltage levels to the gates of drain and source selection transistors, with a first pass voltage to adjacent unselected cells and a second pass voltage to non-adjacent unselected cells, to mitigate channel boosting and reduce electric field strength, thereby preventing hot carrier injection and read disturbances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a read voltage is applied to the selected cell transistor to perform read operations, then the read operation can be executed, but hot carriers are generated causing read disturbance in adjacent cells
Solution Approach 1:
The patent applies different pass voltages to different groups of unselected word lines based on their spatial relationship to the selected cell. Specifically, a first pass voltage is applied to unselected word lines in a first group and a second pass voltage is applied to unselected word lines in a second group, creating localized voltage conditions that prevent hot carrier generation in adjacent cells while maintaining read functionality in the selected cell.
2Reliability
If a high pass voltage is applied to unselected cells to prevent hot carrier injection, then read disturbance is reduced, but the complexity of voltage control increases
Solution Approach 1:
The patent segments the unselected word lines into at least two distinct groups: a first group receiving a first pass voltage and a second group receiving a second pass voltage. This segmentation allows for differentiated voltage control that targets the specific needs of adjacent cells (first group) versus other unselected cells (second group), reducing read disturbance through precise local control.
Solution Approach 2:
Different pass voltages are applied to different groups of unselected word lines based on their spatial relationship to the selected cell. The first pass voltage is applied to unselected word lines in a first group (typically adjacent to the selected cell) and the second pass voltage is applied to unselected word lines in a second group, creating localized voltage conditions that optimize protection against hot carrier effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively suppresses read disturbances by preventing hot carriers from forming, enhancing the reliability and retention characteristics of the flash memory device.
Implementation Method 1
one of them is caused by a hot carrier. Specifically, as shown in FIG. 2, in the case of reading a cell transistor 132, a read voltage Vread of approximately a voltage of 0V is applied to a word line WL2 of the selected cell transistor 132 and a pass voltage Vpass higher than the read voltage Vread, (e.g., approximately 5V) is applied to unselected cells (e.g., the remaining word lines WL3 and WL4 of the remaining cell transistors 133 and 134). However, channel boosting by the pass voltage Vpass applied to the word line WL3 of the cell transistor 133 can occur.
Implementation Method 2
The cell transistor 133 is adjacent to the selected cell transistor 132 and thus a strong horizontal electric field and a strong vertical electric field are formed as indicated by arrows 241 and 242 in the drawing.
Data Source
AI summary
A method of reading a NAND flash memory device includes a cell string having a drain selection transistor, a plurality of memory cells and a source selection transistor which are in series connected to each other. The method comprises the steps of applying a first voltage to a gate of the drain selection transistor in order to turn on the drain selection transistor, applying a read voltage to a gate of a selected memory cell among the plurality of memory cells, and applying first and second pass voltages to gates of unselected memory cells of the plurality of memory cells, wherein the first pass voltage of a relatively high level is applied to the gates of the unselected memory cells which are adjacent to the selected memory cell and wherein the second pass voltage of a relatively high level is applied to the gates of the unselected memory cells which are not adjacent to the selected memory.