NAND Flash Memory Read Disturbance Reduction via Word Line Voltage Control
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Solution Overview
Problem
Conventional NAND flash memories experience increased read disturbance as the number of memory cells in a string grows, leading to inefficiencies in data reading and higher power consumption due to the need for high voltage generation and multiple charge pump stages.
Innovation Solution
A nonvolatile semiconductor memory device and method that fix the voltage of unselected word lines to a predetermined voltage and adjust the voltage of selected word lines during read operations, reducing read disturbance and eliminating the need for high voltage generation, thereby minimizing power consumption and operation time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory cells in a NAND string is increased to expand memory capacity, then the storage capacity is improved, but read disturbance increases
Solution Approach 1:
The patent changes the voltage parameters applied to unselected word lines during read operations. Instead of using conventional high voltages (e.g., 6V) that cause read disturbance, the invention applies a predetermined lower voltage that suppresses the electric field stress on unselected memory cells, thereby reducing read disturbance while maintaining high memory capacity with 64 cells per string
2Productivity
If high voltage is applied to unselected word lines during read operations to switch on unselected memory cells, then reading capability is improved, but power consumption increases
Solution Approach 1:
The patent modifies the voltage parameter applied to unselected word lines from high voltage (6V) to a predetermined lower voltage during read operations. This parameter change reduces the power consumption of the voltage generation circuit and charge pump stages while still enabling effective read operations by maintaining appropriate voltage differentials across the memory cells
Solution Approach 2:
The invention extracts and eliminates the need for complex high voltage generation circuits and multiple charge pump stages by using a simplified voltage scheme where unselected word lines are held at a predetermined voltage level, thereby reducing circuit complexity and power consumption while maintaining reading capability
3Reliability
If high voltage generation circuits and multiple charge pump stages are used to maintain read operations, then reading reliability is improved, but device complexity increases
Solution Approach 1:
The patent removes the complex high voltage generation circuits and multiple charge pump stages from the memory device by adopting a simplified voltage scheme. Unselected word lines are held at a predetermined voltage level during read operations, which eliminates the need for complex voltage step-up circuits while maintaining reading reliability through appropriate voltage differentials
Solution Approach 2:
The predetermined voltage applied to unselected word lines serves multiple functions simultaneously: it prevents read disturbance by reducing electric field stress on unselected memory cells, enables effective read operations by maintaining voltage differentials, and eliminates the need for complex high voltage generation circuits. This multi-functional approach simplifies the overall device architecture
Data Source
AI summary
At the time of reading, an unselected word line voltage is fixed to a first predetermined voltage (0 V or 3 V), and when selecting a word line, a selected word line voltage is set to a second predetermined voltage (−3.5 V or 0 V). This configuration eliminates an application of a pulsed voltage to the word line at the time of reading, making it possible to reduce an influence of read disturbance. In addition, even when a voltage in a range from a power source voltage to a ground voltage or a voltage over the power source voltage is required at the time of reading, it becomes a voltage about 1.5 times an absolute value of the power source voltage. Therefore, a voltage step-up circuit having a large number of stages is not required, and as a result, it is possible to achieve a reduced operation time with a low power consumption.