NAND Flash Page Buffer Layout for Continuous Read ECC

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

NAND flash memory faces challenges in supporting high-speed code shadow applications due to architectural, performance, and data integrity limitations, particularly in managing errors across page boundaries without interrupting continuous read operations.

Innovation Solution

Implementing a partitioned page buffer and cache register system with overlapping ECC processing and status determination, allowing for continuous read operations with error correction across page boundaries without wait intervals, and providing page-by-page ECC status information for enhanced data integrity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If traditional sequential ECC processing is used during page reads, then data integrity is maintained, but read speed is reduced due to wait intervals between pages

Engineering Contradiction:
Improveread speedVSAvoiddata integrity
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent performs ECC processing for subsequent pages in advance during the output time of current page data. Specifically, while first ECC processed data is being output from the first part of the page buffer, the system establishes second ECC processed data in the second part of the page buffer and determines second ECC status in advance. This preliminary action eliminates wait intervals between page reads and maintains continuous data flow without compromising data integrity verification.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements overlapping time relationships between ECC processing operations and data output operations. The ECC engine continuously processes multiple pages simultaneously with the page buffer outputting data, creating a pipelined operation where useful actions (ECC processing and data output) occur continuously without idle wait intervals. This maintains both high read speed and data integrity through uninterrupted verification.

Inventive Principle:
Principle #20Continuity of useful action

2Measurement precision

If ECC processing is performed for each page sequentially, then accurate ECC status is determined, but processing time increases

Engineering Contradiction:
ImproveECC status accuracyVSAvoidprocessing time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent divides the page buffer into a first part and a second part, allowing parallel ECC processing operations. The ECC engine can establish first ECC processed data from a first page in the first part while simultaneously establishing second ECC processed data from a second page in the second part. This segmentation enables multiple ECC status determinations to occur in parallel, maintaining accurate status tracking for each page while reducing total processing time through concurrent operations.

Inventive Principle:
Principle #1Segmentation

3Productivity

If continuous read operations across page boundaries are implemented, then throughput is improved, but error management complexity increases

Engineering Contradiction:
ImprovethroughputVSAvoiderror management complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent introduces a status register as an intermediary component that automatically captures and stores ECC status information for multiple pages during continuous read operations. As the ECC engine determines ECC status for each page, the status register automatically latches this information without requiring complex control logic to track errors across page boundaries. This intermediary simplifies error management while enabling high-throughput continuous reads across multiple pages.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS9367392B2NAND flash memory having internal ECC processing and method of operation thereof
Publication Date: 2016.06.14 WINBOND ELECTRONICS CORP
  • US9367392B2 patent drawing
  • US9367392B2 patent drawing
  • US9367392B2 patent drawing

AI summary

A continuous read operation may be achieved by using a data buffer having a partitioned data register and a partitioned cache register, user configurable internal ECC associated with the cache register, and fast bad block management. During a data read operation, the ECC status may be indicated by ECC status bits. The status (1:1), for example, may indicate for the Continuous Read Mode that the entire data output contains more than 4 bits errors/page in multiple pages. However, one may wish to know the ECC status of each page or of each page partition. For the former, the ECC status for the entire page may be determined and made in the status register at the end of the output of the page. For the latter, the ECC status of each page partition may be determined and output before output of the corresponding page partition.