NAND Flash Read Retry Voltage Adjustment Method
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Solution Overview
Problem
Semiconductor memory devices, particularly NAND flash memory, face challenges in maintaining data reliability over long periods due to electron loss and increased cycling number, which affects programming speed and retention, leading to potential overlap between memory cell distributions.
Innovation Solution
An operating method for semiconductor memory devices that involves performing read operations with adjustable read voltages based on error bit correction, storing read retry numbers in spare cells, and updating these numbers to optimize read operations and reduce read time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the size of memory cell decreases to increase integration, then integration density is improved, but electron loss increases causing distribution overlap and reliability degradation
Solution Approach 1:
The patent applies preliminary action by performing a first read operation with an initial read voltage before the main read operation. This preliminary read identifies error bits in advance, allowing the system to adjust the read voltage accordingly and prevent distribution overlap issues before they affect data integrity. The error bit detection and voltage adjustment happen proactively rather than reactively.
Solution Approach 2:
The patent implements parameter changes by dynamically adjusting the read voltage based on the number of error bits detected. When error bits exceed a threshold, the read voltage is modified (incremented or decremented) to shift the read threshold and resolve distribution overlap. This adaptive parameter adjustment maintains reliability despite memory cell size reduction.
2Productivity
If repeated program/erase operations are performed to increase cycling number, then programming speed is improved, but electron trapping in tunnel oxide layer increases causing threshold voltage shifts
Solution Approach 1:
The patent implements feedback by using error bit detection results from read operations to adjust subsequent read voltages. The system continuously monitors error bits and feeds this information back to modify the read voltage, creating a closed-loop control system that compensates for threshold voltage shifts caused by electron trapping in the tunnel oxide layer.
Solution Approach 2:
The patent applies dynamics by making the read voltage adaptive rather than fixed. The read voltage dynamically changes based on the detected error bit count, allowing the system to respond to varying conditions caused by repeated cycling operations. This dynamic adjustment maintains accurate data retrieval despite threshold voltage drift.
3Reliability
If accurate adjustment of electron storage number is performed to prevent distribution overlap, then data reliability is improved, but read operation complexity and time increase
Solution Approach 1:
The patent applies segmentation by dividing the read operation into two distinct phases: a first read operation that detects error bits, and a second main read operation that retrieves actual data. This segmentation allows error detection and voltage adjustment to occur separately, optimizing the overall read process while maintaining data integrity.
Solution Approach 2:
The patent implements partial action by performing a limited first read operation that only checks for error bits without retrieving complete data. This partial read consumes minimal time and resources, yet provides sufficient information to adjust the read voltage for the main operation, avoiding the need for excessive voltage adjustments during the primary data retrieval.
Data Source
AI summary
An operating method of a semiconductor memory device includes performing a first read operation on main cells of a first page with an initial read voltage, performing a second read operation on the main cells of the first page with a read voltage corresponding to a read retry number when the number of error bits generated as results of performing the first read operation exceeds the number of error-correctable bits, and storing the read retry number in spare cells of the first page while the second read operation is performed, and repeatedly performing the second read operation and repeatedly storing the read retry number until the number of error bits generated as results of performing the second read operation becomes the number of error-correctable bits or less.