NAND Flash Block Read Scheduling for Voltage Stabilization
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Solution Overview
Problem
Conventional NAND flash memory devices experience inefficiencies in data read operations due to the time-consuming stabilization of read and pass voltages during continuous data read operations on multiple memory cell blocks.
Innovation Solution
The memory device and method enable concurrent data read operations on different memory cell blocks by applying read and pass voltages to next blocks in advance, ensuring overlapping but non-overlapping data reading time periods, thereby eliminating waiting times for voltage stabilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If read voltage and pass voltage are applied to each memory cell block sequentially, then voltage stabilization is ensured, but data reading speed decreases due to repeated waiting times
Solution Approach 1:
The patent applies read voltage and pass voltage to the next memory cell block in advance before the current block's data reading is complete. This preliminary action allows the voltage to stabilize beforehand, eliminating the waiting time when switching between blocks while ensuring reliable voltage stabilization is achieved.
Solution Approach 2:
The patent implements continuous data reading operations across multiple memory cell blocks by overlapping the voltage application phase with the data reading phase of other blocks. This continuity eliminates idle waiting periods and maintains constant productive operation throughout the data reading process.
2Speed
If voltage stabilization waiting time is eliminated by concurrent operations, then data reading speed improves, but voltage instability may occur
Solution Approach 1:
By applying voltage to the next block in advance while the current block is being read, the system ensures voltage stabilization occurs during the overlapping time period rather than during active data reading, preventing voltage instability while maintaining high speed.
Solution Approach 2:
The patent divides the memory device into multiple independent memory cell blocks that can operate concurrently. This segmentation allows voltage application and stabilization to occur in parallel with data reading operations on other blocks, eliminating the trade-off between speed and stability.
3Ease of operation
If multiple memory cell blocks are accessed sequentially, then operation simplicity is maintained, but overall reading efficiency decreases
Solution Approach 1:
The patent merges the voltage application operation for the next block with the data reading operation of the current block by timing them to overlap. This combination allows both operations to proceed simultaneously, improving overall reading efficiency while maintaining relatively simple control logic through the controller's coordinated management.
Data Source
AI summary
A data accessing method of a memory device includes the following steps. During a first time period, a read voltage is applied to a first read selected word line in a first memory cell block. During a first data reading time period in the first time period, at least one first memory cell string in the first memory cell block is activated. During a second time period, the read voltage is applied to a second read selected word line in a second memory cell block. The first time period partially overlaps the second time period. During a second data reading time period in the second time period, at least one second memory cell string in the second memory cell block is activated. The first data reading time period does not overlap the second data reading time period.