NAND Flash Read Method Using Unselected Bit Line Voltage

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Solution Overview

Problem

NAND flash memory devices experience read disturb issues due to increased bit line coupling and pass voltage, which affects the accuracy of read operations, especially with multi-level cell structures.

Innovation Solution

Applying a power supply voltage to an unselected bit line to reduce the potential difference between the gate and channel of unselected memory cells, while maintaining a high pass voltage for read operations, thereby reducing the likelihood of read disturb and improving sensing accuracy.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a high pass voltage is applied to unselected word lines to turn on unselected memory cells, then read operation speed is improved, but read disturb occurs due to increased potential difference between gate and channel

Engineering Contradiction:

Improveread operation speedVSAvoidread disturb

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The patent applies different voltage conditions to different bit lines: unselected bit lines are maintained at a higher voltage (e.g., 1V or 2V) while selected bit lines are at 0V. This local voltage differentiation reduces the potential difference between gate and channel for unselected memory cells, thereby reducing read disturb while maintaining high pass voltage for read speed.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent changes the voltage parameter of unselected bit lines from the conventional 0V to a higher voltage level (1V or 2V). This parameter change directly reduces the potential difference across unselected memory cells, mitigating read disturb effects while allowing high pass voltage to be maintained for fast read operations.

Inventive Principle:

Principle #35Parameter changes

2Quantity of substance

If bit line coupling is increased to improve memory density, then device integration is improved, but voltage precharge on unselected bit lines is reduced due to coupling effects

Engineering Contradiction:

Improvememory densityVSAvoidvoltage precharge accuracy

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The patent preemptively compensates for the voltage drop caused by bit line coupling by pre-charging unselected bit lines to a higher voltage level. This preliminary action ensures that even after coupling effects reduce the voltage, unselected memory cells still maintain sufficient potential difference reduction to prevent read disturb.

Inventive Principle:

Principle #9Preliminary anti-action

Data Source

PatentUS7505322B2Method for reading NAND flash memory device using self-boosting

Publication Date: 2009.03.17 SK HYNIX INC

AI summary

A method for reading a NAND flash memory device is provided. The NAND flash memory device includes a first bit line that is selected and a second bit line that is not selected. Each bit line is connected to a cell string including a string selection transistor, a plurality of memory cell transistors, and a source selection transistor connected in series. In the method, first, the first bit line is precharged while power supply voltage is applied to the second bit line. The string selection transistors are turned on and a read voltage is applied to a selected memory cell while a pass voltage is applied to unselected memory cells. The state of the selected memory cell transistor is detected according to whether or not charge precharged on the first bit line has been discharged.