NAND Flash Memory Page-Specific Read Voltage Allocation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing NAND flash memory technologies face challenges in efficiently storing and retrieving multi-bit data due to limitations in read voltage application and data allocation strategies, leading to inefficiencies in data storage and retrieval operations.
Innovation Solution
The memory device employs a controller that applies different numbers of read voltages in read operations for different pages, allowing 5-bit data storage per memory cell and optimizing data allocation across multiple pages, thereby enhancing data retrieval efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional NAND flash memory applies uniform read operations for all pages, then device complexity is reduced, but data retrieval efficiency deteriorates
Solution Approach 1:
The patent divides the read operation into page-specific segments, where each page (Page 0-4) has its own optimized read voltage sequence and timing parameters. The controller identifies which page is being read and applies the corresponding optimized protocol, transforming a uniform read operation into segmented page-specific operations that improve retrieval efficiency while managing complexity through structured organization.
Solution Approach 2:
The patent implements dynamic read voltage selection where the read voltage sequence and timing are adjusted based on the specific page being accessed. Instead of a static uniform read operation, the system dynamically selects from multiple pre-defined read protocols (7-6-6-6-6 pattern for Page 0, 6-7-6-6-6 for Page 1, etc.), allowing the read operation to adapt to page-specific characteristics and optimize performance.
2Quantity of substance
If 5-bit data storage per memory cell is implemented with optimized page allocation, then data storage density increases, but data allocation complexity increases
Solution Approach 1:
The patent applies local quality by assigning different data allocation patterns to different pages. Each page has its own optimized allocation strategy (e.g., Page 0 uses 7-6-6-6-6 read pattern, Page 1 uses 6-7-6-6-6), allowing the system to maximize storage density locally in each page while maintaining overall system organization. This page-specific optimization enables 5-bit per cell storage without requiring uniform complex allocation across all pages.
Solution Approach 2:
The patent employs preliminary action by pre-defining the read voltage sequences and timing parameters for each page before actual data retrieval. The controller has pre-configured the 7-6-6-6-6, 6-7-6-6-6, 6-6-7-6-6, 6-6-6-7-6, and 6-6-6-6-7 patterns in advance, so when a read operation is initiated, the appropriate pre-configured protocol is simply selected and executed, reducing real-time allocation complexity while maintaining optimized data density.
Data Source
AI summary
A memory device includes a first memory cell array and a controller. The first memory cell array includes a plurality of pages, with each of the plurality of pages including a plurality of memory cell transistors configured to store data of a K-value, and K being an integer of 1 or more. The controller writes data into a first page and a second page included in the plurality of pages of the first memory cell array without executing a verify read during a write operation in response to one command set including a write command and data.