3D NAND Flash Memory Read Voltage Adjustment
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Solution Overview
Problem
Three-dimensional NAND flash memory devices face reliability issues due to charge leakage between adjacent memory cells, affecting data storage accuracy and longevity, as electrons and electron holes combine across shared charge storage layers, altering the electric charge distribution and reducing data integrity over time.
Innovation Solution
The memory device employs a controller that selects adjustment values based on read data from one memory cell to read data from another using specific read voltages, accounting for the threshold voltage states of adjacent cells to mitigate charge leakage effects and enhance data accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional NAND flash memory structure is used to increase storage capacity, then storage density is improved, but charge leakage between adjacent memory cells increases
Solution Approach 1:
The patent applies preliminary action by performing a read operation on a first memory cell before reading the second memory cell. Based on the read result from the first cell, an adjustment value is determined and applied to compensate for charge leakage effects before reading the second cell. This proactive compensation approach prevents charge leakage from degrading data integrity, resolving the contradiction between high storage density and data reliability in three-dimensional NAND flash memory structures.
2Speed
If read voltage is increased to improve reading speed, then data reading speed is improved, but charge leakage between adjacent cells increases
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the read voltage based on the state of adjacent memory cells. Instead of using a fixed high read voltage that causes charge leakage, the system modifies the read voltage parameter according to the read result from the first memory cell. This adaptive voltage adjustment maintains fast reading speeds while compensating for charge leakage effects, resolving the contradiction between reading speed and charge leakage.
3Quantity of substance
If adjacent memory cells are placed closer to increase density, then storage density is improved, but charge leakage between cells increases
Solution Approach 1:
The patent applies feedback by using the read result from the first memory cell to determine an adjustment value that compensates for charge leakage affecting the second memory cell. This feedback mechanism allows the system to detect and correct charge leakage effects caused by closely spaced cells, enabling high storage density while maintaining data reliability through continuous monitoring and adjustment based on adjacent cell states.
Data Source
AI summary
A memory device of an embodiment includes a memory cell array and a controller. In the memory cell, data is written per page unit and is erased per block which is a multiple the page unit of a natural number of two or more. The block includes memory strings, each including memory cells capable of storing data of one or more bits with a threshold voltage indicative of an erase state in which data is erased and one or more threshold voltages which are higher than the voltage indicative of the erase state and indicate written states in which data is written. The controller selects one of adjustment values of positive and negative values based on data read from a first memory cell of the memory cells, and reads data from a second memory cell of the memory cells using the selected adjustment value and a first read voltage.