NAND Flash Memory Readout Voltage Grouping for Source Side Effect
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Solution Overview
Problem
NAND flash memory experiences readout errors due to the source side effect after a large number of write and erase cycles, where the increased channel resistance leads to misreading data '1' as data '0' due to the back pattern effect and body effect of metal oxide semiconductor field effect transistors.
Innovation Solution
The reading method involves dividing word lines into groups and adjusting the readout voltage and pass voltage accordingly, with the readout voltage increasing towards the bit line side and the pass voltage dynamically set based on the position of the selected word line to reduce errors. Specifically, the readout voltage applied to the selected word line increases towards the bit line side, and the readout pass voltage applied to non-selected word lines is set to be greater between the selected word line and the source line compared to between the selected word line and the bit line.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fixed readout voltage is applied to all word lines, then the reading operation is simple, but readout errors occur due to source side effect and back pattern effect after numerous write and erase cycles
Solution Approach 1:
The patent segments the word lines into multiple groups (first group, second group, third group) based on their position relative to the bit line. Different readout voltages are applied to different groups, with voltages increasing from the first group to the third group. This segmentation allows compensation for the source side effect and back pattern effect that vary by position, thereby improving readout accuracy without requiring completely different voltage control schemes for each word line.
Solution Approach 2:
The patent applies different readout voltages to different groups of word lines based on their local characteristics. Word lines closer to the bit line (third group) receive higher readout voltages to compensate for the increased threshold voltage caused by source side effect and back pattern effect, while word lines farther away (first group) receive lower voltages. This local quality approach ensures each region operates optimally, improving overall readout reliability.
2Reliability
If readout voltage is increased to compensate for threshold voltage shift, then readout accuracy improves, but power consumption increases
Solution Approach 1:
The patent applies partial compensation by dividing word lines into groups and applying different voltage levels rather than uniformly increasing voltage across all word lines. Only the third group of word lines (closest to bit line) receives the highest voltage, while the first group receives the lowest voltage. This partial action approach compensates for the threshold voltage shift where needed while minimizing unnecessary power consumption in regions where compensation is less critical.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces readout errors by offsetting the increased threshold voltage of memory cells near the bit line, maintaining a threshold margin and minimizing misreadings after numerous write and erase cycles.
Implementation Method 1
due to the body effect of the metal oxide semiconductor field effect transistor of the memory cell i
Implementation Method 2
The NAND flash memory has a back pattern effect, which enables the threshold Vt of the read memory cell to have a strong dependence on the data of other memory cells of the NAND string
Data Source
AI summary
A semiconductor memory device capable of reducing failure caused by a source side effect after a large number of W/E cycles is provided. A reading method of a NAND flash memory includes: dividing multiple word lines connected to each memory cell of a NAND string into a group 1 of word lines WL0 to WLi−1, a group 2 of word lines WLi to WLj, . . . , a group y of word lines WLj+1 to WLk−1, and a group x of word lines WLk to WLn, presetting a relationship that each readout voltage (Vread1, Vread2, . . . , Vready, and Vreadx) corresponding to each group increases toward a bit line side, and applying a readout voltage to a selected word line according to the relationship.