NAND Flash Redundancy Cache for Yield and Speed
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Solution Overview
Problem
Existing redundancy methods in semiconductor memories, such as NAND flash memory, face inefficiencies in defect compensation and yield rate improvement due to uneven allocation of redundancy bits, leading to decreased chip yield and operational speed.
Innovation Solution
A semiconductor storing device with a storing array and redundancy area, utilizing a column selecting mechanism, redundancy information storage, and an error correction mechanism that transforms defect data into redundancy data, allowing for efficient compensation and high-speed data reading by alternately outputting core and redundancy data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundancy bits are allocated to compensate defect elements, then the yield rate increases, but the reading speed decreases due to sequential processing requirements
Solution Approach 1:
The patent pre-loads redundancy data into a dedicated redundancy cache register before it is needed for defect compensation. This preliminary action allows the redundancy data to be ready and available when defect elements need to be compensated, eliminating the sequential waiting time that previously reduced reading speed. The control circuit activates the redundancy cache register and prepares redundancy data in advance, so that when a defect is detected, the replacement can occur without delaying the overall read operation.
2Reliability
If redundancy data is stored in the main cache register, then defect compensation is possible, but the cache register capacity for core data is reduced
Solution Approach 1:
The patent divides the cache register system into two separate functional units: a main cache register for storing core data and a dedicated redundancy cache register for storing redundancy data. This segmentation allows each register to be optimized for its specific purpose without compromising the other. The main cache register maintains full capacity for core data, while the redundancy cache register provides dedicated space for redundancy information, ensuring that defect compensation capabilities are preserved without reducing the capacity available for primary data storage.
3Reliability
If defect elements are compensated using existing redundancy methods, then some defects are corrected, but the compensation efficiency is low due to uneven allocation of redundancy bits
Solution Approach 1:
The patent implements a control circuit that dynamically identifies the specific location and pattern of defect elements in the array, and then selectively activates only the corresponding redundancy cache register entries needed for compensation. Instead of uniformly allocating redundancy resources across the entire array, the system applies local quality by matching redundancy resources precisely to where defects actually occur. This targeted approach significantly improves compensation efficiency by avoiding the waste of redundancy bits on defect-free regions while ensuring adequate coverage for defective areas.
Data Source
AI summary
A semiconductor storing device and a redundancy method thereof are provided. The semiconductor storing device is for example a NAND flash memory, which includes: a storing array including a storing area and a redundancy storing area with a redundancy element; a page buffer; a row selecting circuit; an ECC circuit; and an I/O buffer. The row selecting circuit transforms defect data included in core data retained by a cache register into redundancy data retained by a redundancy cache register, and provides the transformed data to the ECC circuit, and the data corrected by the ECC circuit as the core data is written to the cache register again. During this period, the row selecting circuit outputs the corrected data retained in the cache register to the I/O buffer.