NAND Flash Refresh Control Using Soft-Value Likelihood Reads
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Solution Overview
Problem
The increasing probability of fail bits in NAND cell type flash memory due to miniaturization leads to reduced yield and data reliability, with existing refresh operations being time-consuming and inefficient, especially in areas with few errors, and error-correction methods struggling to determine when refresh is necessary.
Innovation Solution
A non-volatile semiconductor memory device with a memory cell array capable of storing multi-value data, utilizing a sense amplifier circuit, word-line control circuit, likelihood calculation circuit, error correction circuit, and refresh control circuit to apply soft-value read voltages and calculate likelihood values for precise error correction and timed refresh operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If refresh operation is performed in all memory areas, then data reliability is improved, but operation time increases significantly
Solution Approach 1:
The memory cell array is divided into multiple blocks, and the refresh operation is segmented to process only specific blocks that require refresh based on error correction results, rather than refreshing the entire memory array uniformly
Solution Approach 2:
Different refresh strategies are applied to different blocks based on their individual error characteristics. Blocks with high error rates receive refresh operations while blocks with low error rates are skipped, making the refresh operation locally optimized rather than uniformly applied
2Reliability
If refresh operation is performed in all memory areas, then data reliability is improved, but unnecessary stress is applied to areas with small error amounts
Solution Approach 1:
The refresh operation is selectively applied only to blocks that exhibit high error rates, while blocks with low error rates are excluded from refresh operations, thereby avoiding unnecessary stress on healthy memory cells
Solution Approach 2:
The system uses feedback from the error correction circuit regarding the number of corrected errors in each block to determine which blocks require refresh operations, enabling intelligent decision-making about where refresh is necessary
3Productivity
If error correction count is used to determine refresh timing, then refresh operation can be optimized, but iterative decoding methods cannot provide error correction counts
Solution Approach 1:
An intermediary parameter (likelihood value) is introduced to replace the direct error correction count. The likelihood value, calculated from soft read values, serves as a proxy indicator of error severity that enables refresh decision-making without requiring explicit error correction counts from iterative decoders
Solution Approach 2:
The system changes from using discrete error correction counts to using continuous likelihood values derived from soft read values, enabling more nuanced assessment of error conditions and more precise refresh timing decisions
Data Source
AI summary
This memory device comprises a word-line control circuit applying a read voltage and a soft-value read voltage as a word line voltage to a word line to generate soft-values. The soft-value read voltage is between an upper limit and a lower limit of each of plural threshold voltage distributions. A likelihood calculation circuit calculates a likelihood value of data stored in a memory cell based on the soft-value. An error correction circuit executes data error correction for the data read from the memory cell based on the likelihood value. A refresh control circuit controls a timing of a refresh operation for the memory cell based on the soft-value or the likelihood value.