NAND Flash Controller Buffering for Repeated Bit Error Correction
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Solution Overview
Problem
Multi-Level Cell (MLC) NAND Flash memories face increased bit error rates due to high bit capacity, leading to reduced storage capacity as unrecoverable error bits result in 'bad blocks' that cannot be used, necessitating a method to effectively correct repeated error bits.
Innovation Solution
A controller system that generates commands for non-volatile memory, combines first page data with error bits and second page data containing original bits for error correction, using Error Correction Codes (ECC) like Reed-Solomon and Bose-Ray-Chaudhuri-Hocquenghem codes to replace and correct error bits based on an error location table.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If MLC NAND Flash uses higher bit capacity per cell (3 bits or 4 bits), then storage capacity increases, but bit error rate increases leading to more bad blocks
Solution Approach 1:
The patent segments the data retrieval process into multiple stages: first retrieving data from the main region, then selectively retrieving only the specific columns containing error bits from the spare region based on error location information. This segmentation allows targeted error correction without requiring the entire spare region to be always accessible, thus maintaining high storage capacity while improving reliability.
Solution Approach 2:
The patent performs preliminary action by pre-storing error location information and corresponding correct data in the spare region during the programming phase. This allows the controller to quickly identify and correct error bits during read operations without performing complex real-time analysis, thereby maintaining high reliability while preserving storage capacity.
2Reliability
If spare region is used to correct error bits, then reliability improves, but main region capability is reduced
Solution Approach 1:
The patent applies local quality by using different parts of the spare region for different purposes: some columns store error location information while other columns store actual correction data. This localized functional differentiation allows the spare region to provide comprehensive error correction support without uniformly reducing the main region's storage capability across all columns.
Solution Approach 2:
The patent introduces error location information as an intermediary element that mediates between the main region data and the spare region correction data. This intermediary allows the system to efficiently identify which specific error bits need correction and retrieve only the necessary correction data, thereby maintaining high reliability while minimizing the impact on main region capability.
3Reliability
If ECC and redundant column are used to correct error bits, then reliability improves, but storage capacity is reduced
Solution Approach 1:
The patent applies partial action by implementing error correction only for the specific columns identified as containing errors, rather than applying correction mechanisms to all data. This selective approach uses the Error Correction Code and redundant columns only where needed, maintaining reliability for affected data while preserving storage capacity for the majority of error-free data.
Data Source
AI summary
The present disclosure provides a controller which comprises a command generator configured to generate a command to non volatile memory, and buffer configured to receive a first data and a second data and configured to combine the first data and the second data, an ECC unit configured to perform the ECC decoding. And the first page data may include at least one error bit corresponding to an error location table and the second page data may include at least one original bit which can be replaced with the error bit. The buffer may replace the at least one error bit with the said at least one original bit. The error location table may save information of location for the repeated error bit.