NAND Flash Reset Control via Decoupling Circuit
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current SSD initialization processes are hindered by unreliable determination of NAND flash device reset completion, leading to significant delays due to shared control signals and variability in reset times, which can result in misinterpretation of residual capacitance as successful reset.
Innovation Solution
A controller circuit activates a decoupling circuit to remove residual capacitance from the data bus after issuing a reset command, ensuring accurate determination of the NAND device's operational readiness by reading all zeros if not ready, thereby preventing further commands from being issued prematurely.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the controller waits for a fixed time period after issuing a reset command before reading status, then the initialization process is simplified, but residual capacitance on the data bus is misinterpreted as successful reset completion
Solution Approach 1:
The decoupling circuit is activated before the status read operation to preemptively remove residual capacitance from the data bus. This preliminary action ensures that when the status is read after the wait period, the data bus is in a known clean state, preventing misinterpretation of residual capacitance as successful reset completion.
2Productivity
If the controller reads status immediately after the wait period, then initialization speed is improved, but commands may be issued prematurely before the NAND device is truly ready
Solution Approach 1:
The decoupling circuit acts as an intermediary between the controller and the NAND device during the status read operation. By actively managing the data bus state through controlled capacitance removal, it provides accurate status information to the controller, enabling reliable determination of when the NAND device is truly ready for command execution.
3Device complexity
If shared control signals are used for multiple NAND devices, then device complexity is reduced, but reset completion status becomes unreliable due to signal sharing and variability
Solution Approach 1:
The decoupling circuit provides localized control over the data bus state for each status read operation. By actively managing capacitance at the specific location where status is being read, it ensures accurate detection of reset completion status even when shared control signals are used across multiple NAND devices with varying reset times.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method ensures reliable initialization by guaranteeing that only valid data are read from the NAND device, reducing initialization delays and preventing incorrect command execution during the reset sequence.
Implementation Method 1
activating a decoupling circuit coupled between the data bus and a reference line at a reference voltage level to remove capacitance from the data bus
Data Source
AI summary
Method and apparatus for managing a non-volatile memory (NVM). In some embodiments, a memory module has a memory module electronics (MME) circuit configured to program data to and read data from solid-state non-volatile memory cells of the NVM. A controller is adapted to communicate commands and data to the MME circuit via an intervening data bus. The controller operates to reset the MME circuit by issuing a reset command to the MME circuit over the data bus, activating a decoupling circuit coupled between the data bus and a reference line at a reference voltage level to remove capacitance from the data bus resulting from the reset command, and subsequently sensing a voltage on the data bus. In some cases, multiple MME circuits and NVMs may be arranged on a plurality of flash dies which are concurrently reset by the controller.