NAND Flash Row Decoder Segmentation for Bad Block Relief
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Solution Overview
Problem
In three-dimensional stacked NAND flash memory devices, the high bit density and large block capacity lead to a significant reduction in available capacity due to bad blocks, where short circuits between adjacent word lines render entire blocks unusable, resulting in a substantial loss of storage capacity.
Innovation Solution
The implementation of a row decoder that divides word lines into logical blocks, using latch circuits to store flags indicating bad blocks, allowing only one logical block to be determined as failed while the other remains operational, thereby preventing the entire physical block from being rendered unusable.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the entire physical block is treated as a single unit, then the block capacity is maximized, but a short circuit between adjacent word lines renders the entire block unusable, causing significant capacity loss
Solution Approach 1:
The physical block is divided into multiple logical blocks, each with its own row decoder and latch circuit. When a short circuit occurs in one logical block, only that specific logical block is marked as bad and excluded from operation, while other logical blocks within the same physical block remain functional. This segmentation prevents the entire block from becoming unusable due to a localized failure.
2Loss of substance
If the row decoder divides word lines into logical blocks with separate latch circuits, then the failure relief efficiency is improved by reducing unusable capacity, but the device complexity increases
Solution Approach 1:
The row decoder is segmented into multiple independent units, each responsible for a specific logical block. Each unit includes its own latch circuit for tracking bad blocks. This segmentation allows parallel operation of multiple logical blocks and enables independent failure management, reducing the impact of bad blocks on overall capacity while maintaining manageable complexity through modular design.
Data Source
AI summary
According to one embodiment, a non-volatile semiconductor memory device includes a memory cell array and a row decoder. The memory cell array has NAND strings as a physical block, and word lines respectively connected to memory cells included in the NAND strings. The row decoder includes latch circuits and a drive circuit. When a failure exists within a corresponding first logical block, the latch circuits store a flag indicating the failure. The drive circuit inhibits driving of the word lines belonging to the first logical block when the flag is stored in the latch circuit corresponding to the first logical block to which the selected word lines belong, and allows the driving of the word lines belonging to the physical block including the first logical block when the flag is not stored in the latch circuit corresponding to the first logical block to which the selected word lines belong.