NAND Flash Row Decoder Area Reduction via Segmentation
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Solution Overview
Problem
The miniaturization of NAND type flash memory devices leads to an increase in the number of memory cells, which in turn results in a larger area for the row decoder, posing a challenge in efficient layout and operation.
Innovation Solution
The implementation of a row decoder configuration that includes shared boost circuits and local row decoders across sub-row decoders, with transfer transistors disposed in a matrix layout and adjacent regions to reduce the overall area occupied by the decoder, allowing for efficient voltage supply and block selection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory cells in one NAND string is increased to achieve miniaturization, then the storage capacity is improved, but the area of the row decoder increases
Solution Approach 1:
The row decoder is divided into multiple sub-row decoders, each responsible for a specific portion of the memory cell array. This segmentation allows the decoder to be distributed across different regions rather than concentrated in one large block, reducing the area required for each sub-decoder while maintaining the ability to address all memory cells.
Solution Approach 2:
The transfer transistors are arranged in a matrix pattern where smaller transistor units are nested within a larger structural framework. This nested arrangement allows efficient use of space by filling gaps and utilizing residual regions, thereby reducing the overall area occupied by the row decoder while maintaining full functionality.
2Quantity of substance
If the number of memory cells is increased to improve storage capacity, then the device density is improved, but the layout complexity of the row decoder increases
Solution Approach 1:
By segmenting the row decoder into sub-row decoders, the layout complexity is distributed across multiple smaller, more manageable units. Each sub-decoder has a simpler structure that is easier to design and manufacture, while the collective system maintains the complexity needed to address the increased number of memory cells.
Solution Approach 2:
The transfer transistors are arranged in a matrix pattern, transitioning from a linear or sequential arrangement to a two-dimensional matrix structure. This dimensional change allows for more compact packing and reduces layout complexity by utilizing spatial relationships in multiple directions simultaneously.
3Area of stationary object
If the row decoder area is reduced to improve device compactness, then the device density is improved, but the voltage supply capability may be compromised
Solution Approach 1:
Adjacent sub-row decoders share common boost circuits, merging their voltage generation capabilities. This merging allows the reduced-area sub-decoders to collectively provide sufficient voltage supply capability by pooling resources, ensuring that the reduced area does not compromise the ability to supply required voltages to all memory cells.
Solution Approach 2:
The boost circuits are designed to serve multiple sub-row decoders simultaneously, making them universal components that perform voltage generation for multiple functions. This multi-functionality allows the row decoder to maintain adequate voltage supply capability despite the reduced area of individual sub-decoders.
Data Source
AI summary
This nonvolatile semiconductor memory device comprises: a memory cell array configured having a plurality of blocks arranged therein, each of the blocks configured as an arrangement of NAND cell units, each of the NAND cell units configured having a plurality of electrically rewritable memory cells and a select transistor connected in series; and a row decoder configured to select anyone of the blocks of the memory cell array and supply to any one of said blocks a voltage required in various kinds of operations. The row decoder comprises: a plurality of first transfer transistors each disposed in a first region and connected to any one of the memory cells; and a plurality of second transfer transistors each disposed in a second region and connected to the select transistor, the second region being a residual region of the first region.