NAND Flash Multi-Level Row Decoding for Wear Distribution
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Solution Overview
Problem
Conventional NAND flash memory devices face limitations such as the need for erasing on a per-block basis, limited endurance due to a restricted number of erase-program cycles, and an inefficient data management system that leads to uneven wear across cells, resulting in premature device failure and reduced lifespan.
Innovation Solution
Implementing a NAND flash memory core with multi-level row decoding, allowing for erasure at the sector level and read/write operations at the row level within a sector, which reduces unnecessary program operations and extends device lifetime by evenly distributing usage across cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If erasing is performed on a per-block basis, then the memory structure is simple to manage, but the device lifespan is reduced due to limited erase-program cycles and uneven wear distribution
Solution Approach 1:
The patent divides a block into multiple sub-blocks, allowing independent erasure of individual sub-blocks rather than requiring erasure of the entire block. This segmentation enables more granular control over erase operations, distributing wear more evenly across the memory device and extending overall lifespan while maintaining manageable complexity through hierarchical organization.
Solution Approach 2:
The patent implements different erasure granularities for different regions of the memory block. By allowing erasure at the sub-block level in certain regions while maintaining block-level erasure in others, the system optimizes wear distribution locally where it is most needed, thereby extending device lifespan without uniformly increasing system complexity.
2Productivity
If read and program operations are performed on a per-page basis, then data access efficiency is improved, but unnecessary program operations occur during block copy leading to increased wear
Solution Approach 1:
The patent segments blocks into sub-blocks that can be independently managed for erase operations. During block copy operations, only the necessary sub-blocks are erased and reprogrammed rather than copying entire blocks, reducing unnecessary program operations and distributing wear more evenly while maintaining efficient page-level data access.
Solution Approach 2:
The patent performs partial erasure and programming operations on only the necessary sub-blocks during block copy operations rather than processing entire blocks. This partial action approach minimizes unnecessary program operations that contribute to wear, thereby improving device endurance while preserving efficient data access capabilities.
3Reliability
If sophisticated data structures and algorithms are implemented for data management, then data integrity is improved, but device complexity increases
Solution Approach 1:
The patent uses segmentation of blocks into sub-blocks as a structural organization method that simplifies data management compared to sophisticated algorithms. This hierarchical structure enables straightforward tracking and management of erased and programmed regions, maintaining data integrity through clear state management while avoiding the complexity of advanced data structures and algorithms.
Data Source
AI summary
A NAND flash memory device is disclosed. The NAND flash memory device includes a NAND flash memory array defined as a plurality of sectors. Row decoding is performed in two levels. The first level is performed that is applicable to all of the sectors. This can be used to select a block, for example. The second level is performed for a particular sector, to select a page within a block in the particular sector, for example. Read and program operations take place to the resolution of a page within a sector, while erase operation takes place to the resolution of a block within a sector.