NAND Flash Memory Operation Instruction Scheduling via Hardware Arbitration
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Solution Overview
Problem
Existing NAND flash memory devices face performance limitations in high-capacity, high-speed applications due to the inefficiencies of software-based operation instruction scheduling, which cannot meet the increasing demands of Input/Output Operations Per Second (IOPS) and bandwidth utilization.
Innovation Solution
The method involves task decomposition of operation instructions into multiple tasks, with each task being sent to a corresponding task queue and then to an arbitration queue based on type, where a NAND interface is scheduled according to priority, utilizing a task generation module, task management module, and task arbiter to optimize resource management and scheduling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If software is used for scheduling operation instructions, then flexibility and ease of modification are improved, but performance and IOPS throughput deteriorate due to processing delays
Solution Approach 1:
The patent replaces the software-based scheduling system with a hardware-based scheduling circuit. The controller includes a scheduling module that directly schedules operation instructions in hardware, eliminating the performance bottlenecks of software processing while maintaining scheduling flexibility through configurable hardware logic. This substitution of mechanical/software system with hardware system resolves the contradiction between flexibility and performance.
2Quantity of substance
If multiple NAND dies are connected to one interface to increase storage capacity and bandwidth utilization, then storage capacity and interface bandwidth utilization are improved, but scheduling complexity increases
Solution Approach 1:
The patent segments the scheduling process into distinct phases: operation instruction generation, validation, and execution scheduling. The controller divides multiple NAND dies into independently addressable units with dedicated task queues, allowing parallel scheduling of operations across different dies. This segmentation reduces scheduling complexity by breaking down the monolithic scheduling problem into manageable, independent sub-tasks that can be processed concurrently.
Solution Approach 2:
The patent implements preliminary validation and decomposition of operation instructions before scheduling. The controller validates instruction sequences and decomposes complex operations into atomic tasks in advance, organizing them in task queues ready for execution. This preliminary processing reduces the complexity of real-time scheduling by pre-preparing standardized, validated instruction units that can be quickly dispatched to multiple NAND dies.
3Quantity of substance
If page size is increased to improve storage capacity, then storage capacity is improved, but access time increases
Solution Approach 1:
The patent segments large-page storage operations into smaller, manageable instruction units that can be processed in parallel. By dividing large page access operations into atomic tasks that can be scheduled across multiple NAND dies, the system maintains high storage capacity while reducing effective access time through parallel processing of segmented operations.
Solution Approach 2:
The patent dynamically adjusts scheduling parameters and operation sequencing to optimize access patterns. By changing the parameters of instruction scheduling, such as interleaving read/write operations and adjusting task priority based on operation type, the system achieves faster effective access times for large-page storage while maintaining full storage capacity utilization.
Data Source
AI summary
The present invention discloses an operation instruction scheduling method and device for a NAND flash memory device. The method comprises: performing task decomposition on the operation instruction of the NAND flash memory device, and sending an obtained task to a corresponding task queue; sending a current task to a corresponding arbitration queue according to a task type of the current task in the task queue; and scheduling a NAND interface for a to-be-executed task in the arbitration queue according to priority information of the arbitration queue. Embodiments of the present invention can efficiently realize operation instruction scheduling of a NAND flash memory device, improve flexibility of operation instruction scheduling of the NAND flash memory device, and improve overall performance of the NAND flash memory device.