NAND Flash Memory Read Control Using Segmented Page Buffers
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Solution Overview
Problem
NAND flash memories have slower read and write speeds and lower reliability compared to NOR flash memories, primarily due to their multi-level cell structure, which affects their performance in storage applications.
Innovation Solution
A control method is introduced that optimizes read and write operations by identifying and recording the values of most significant bits and neighboring bits in NAND flash memory storage units, utilizing preset voltage levels to determine bit values and employing page buffers to manage data output efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If NAND flash memory uses multi-level cell structure to increase capacity, then storage capacity is improved, but read and write speeds deteriorate
Solution Approach 1:
The patent segments the read operation into two distinct phases: first reading the most significant bit (MSB) and storing it in a first page buffer, then reading the neighboring bit and storing it in a second page buffer. This segmentation allows the memory system to handle multi-level cell data in manageable chunks, improving overall read speed by enabling parallel processing and reducing bottlenecks in the data retrieval process.
2Quantity of substance
If NAND flash memory stores various bits per storage unit to increase capacity, then storage capacity is improved, but reliability deteriorates
Solution Approach 1:
The patent applies preliminary action by first reading and storing the most significant bit (MSB) in a dedicated first page buffer before reading the neighboring bit. This preliminary separation allows the system to process and potentially verify the more critical MSB data first, establishing a reliable foundation before handling additional bit information, thereby maintaining higher reliability in multi-level cell operations.
3Reliability
If conventional read method stores all data in internal cache before output, then data integrity is improved, but read time increases
Solution Approach 1:
The patent segments the data storage and retrieval process by creating separate page buffers for different bit types (MSB in first page buffer, neighboring bit in second page buffer) rather than storing all data uniformly in a single internal cache. This segmentation enables selective and parallel data output, maintaining data integrity through structured organization while significantly reducing read time by avoiding sequential access bottlenecks.
Solution Approach 2:
The patent introduces a new dimensional approach to data buffering by organizing data in multiple parallel buffers (first page buffer for MSB, second page buffer for neighboring bit) rather than a single sequential cache structure. This multi-dimensional buffer architecture allows simultaneous data preparation and retrieval operations, improving both data integrity through structured organization and read speed through parallel processing capabilities.
Data Source
AI summary
A control method for a memory is provided. The memory includes a plurality of storage units, each storing a plurality of bits. In a read mode, a read command is provided to the memory. The value of a most significant bit (MSB) of each storage unit is obtained and recorded. The value of the most significant bits is output. The value of a neighboring bit of each storage unit is obtained and recorded. The neighboring bit neighbors the most significant bit. The value of the neighboring bits is output.