NAND Flash Memory Continuous Readout via Segmented Arrays
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Solution Overview
Problem
Existing NAND flash memory technologies face challenges in achieving high-speed continuous readout while minimizing peak current and ensuring data integrity, particularly when using low-frequency external clock signals, which can lead to data destruction and instability due to asynchronous clock signals and large peak currents.
Innovation Solution
The method involves independently reading and holding half pages from separate memory cell arrays, transferring and outputting data in synchronization with a clock signal, and performing error checking and correction on each half page, allowing for continuous readout without frequency restrictions and reducing peak current by precharging bit lines separately.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If continuous readout is performed using a single memory cell array and latch, then the readout speed is limited by the clock signal frequency and data transfer timing, but if multiple memory cell arrays and latches are used with independent readout, then the readout speed is no longer restricted by clock signal frequency
Solution Approach 1:
The patent divides the memory system into two independent memory cell arrays (first and second arrays) with separate readout paths, each having its own latch (L1 and L2). This segmentation allows parallel independent readout operations, eliminating the clock frequency bottleneck that limits single-array continuous readout.
Solution Approach 2:
The patent combines multiple memory cell arrays and latches to work together in a coordinated manner. The first latch L1 reads from the first array while the second latch L2 reads from the second array, and they are merged through the data transfer circuit to provide continuous data stream output.
2Reliability
If data is transferred between latches during continuous readout, then data integrity may be compromised due to asynchronous clock signals and timing conflicts, but if separate independent readout paths are used, then data integrity is maintained
Solution Approach 1:
The patent segments the data path into two independent channels: first array → L1 and second array → L2. Each channel operates independently with its own timing, eliminating data corruption issues that arise from transferring data between latches driven by asynchronous clock signals.
Solution Approach 2:
The data transfer circuit acts as an intermediary that receives data from both L1 and L2 and outputs them in sequence. This mediator coordinates the output timing without requiring data transfer between the latches themselves, thus maintaining data integrity while enabling continuous readout.
3Reliability
If bit lines are precharged simultaneously for full page readout, then large peak current is generated causing voltage drops and instability, but if bit lines are precharged separately for half pages, then peak current is reduced and voltage stability is improved
Solution Approach 1:
The patent segments the readout operation into two independent half-page readouts, one from the first array and one from the second array. Each array precharges its own bit lines separately, which divides the total precharge current by half, reducing peak current and preventing voltage drops that cause instability.
Solution Approach 2:
While the first array is performing its half-page readout and bit line precharge, the second array simultaneously performs its own half-page readout and precharge. This continuous parallel operation maintains high productivity despite the segmented approach, as both arrays work concurrently without waiting for each other.
Data Source
AI summary
A semiconductor apparatus and a continuous readout method for improving prior continuous readout are provided. A flash memory includes: a NAND memory cell array, an input/output circuit, an ECC circuit, a controller, a word-line selection circuit, a page buffer/readout circuit, and a row selection circuit. When performing the continuous readout of pages, the controller performs an array readout of a first half page of a selection page on the memory cell array and an array readout of a second half page of the selection page on the memory cell array independently, and continuously outputs the respectively read data of the half pages in synchronization with a clock signal.