NAND Flash Memory Cell Programming Using Segmented Sense Lines
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Solution Overview
Problem
As NAND flash memory scales, parasitic capacitance coupling between adjacent memory cells increases, leading to wider threshold voltage distributions and degraded programming performance, especially in multi-level cell (MLC) devices, which can result in erroneous data reads and require more complex read circuitry.
Innovation Solution
Implementing a method that uses common sensing voltage levels to program and sense different states in memory cells, reducing the number of sensing cycles and simplifying circuitry by interweaving cells with varying numbers of digits on alternating sense lines, thereby mitigating floating gate-to-floating gate interference effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If NAND flash memory is scaled to increase memory density, then memory capacity increases, but parasitic capacitance coupling between adjacent memory cells increases causing wider threshold voltage distributions and degraded programming performance
Solution Approach 1:
The patent divides the memory array into alternating even and odd sense line groups, with each group containing memory cells coupled to respective sense lines. This segmentation allows independent programming of adjacent cells in different groups, isolating the programming operation to single cells rather than requiring simultaneous programming of multiple adjacent cells, thereby reducing parasitic capacitance coupling effects.
Solution Approach 2:
The patent implements periodic programming by alternating between programming cells on even sense lines and cells on odd sense lines. This periodic action ensures that when one group of cells is being programmed, the other group remains in a non-programming state, reducing interference from parasitic capacitance coupling and maintaining tighter threshold voltage distributions.
2Quantity of substance
If multiple level cell (MLC) programming is implemented to store multiple digits per cell, then memory density increases, but floating gate-to-floating gate interference effects are greatly increased causing erroneous data reads
Solution Approach 1:
The patent segments the MLC array into alternating even and odd sense line groups, allowing selective programming of individual cells or small subsets of cells. This segmentation reduces the simultaneous programming of multiple adjacent cells, thereby reducing floating gate-to-floating gate interference effects that cause erroneous data reads in MLC devices.
Solution Approach 2:
The patent uses periodic programming actions by alternating between even and odd sense line groups. This periodic approach ensures that when one group is programmed, the other group is not being programmed, reducing cumulative interference effects and improving data read accuracy in high-density MLC configurations.
3Reliability
If programming methods are designed to combat coupling effects in MLC devices, then interference effects are reduced, but read performance is degraded and read circuitry becomes more complex
Solution Approach 1:
The patent segments the memory array into even and odd sense line groups that can be independently programmed. This segmentation allows the use of simple, uniform read circuitry that senses cells in a straightforward manner, while the programming complexity is isolated to the control logic that manages alternating programming sequences, rather than requiring complex read circuitry.
Solution Approach 2:
The patent implements periodic programming sequences that alternate between even and odd sense line groups. This periodic approach maintains simple read circuitry by ensuring that during read operations, the memory array is in a stable, non-programming state, eliminating the need for complex read circuitry designed to operate during or immediately after programming.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves read performance and reduces the complexity of sensing circuitry, allowing for more efficient operation of multilevel memory cells by using fewer sensing voltage levels and reducing adverse interference effects between adjacent cells.
Implementation Method 1
parasitic capacitance coupling between adjacent memory cell floating gates becomes a problem
Data Source
AI summary
Methods, devices, modules, and systems for operating memory cells are taught. A method for operating memory cells includes programming at least one of the memory cells to one of a number of states. Operating memory cells also includes programming at least another one of the memory cells, which is adjacent to the programmed at least one of the memory cells, to one of a different number of states. Operating memory cells also includes sensing non-erased states of the memory cells using at least one common voltage level.