NAND Flash Select Gate Line Voltage Control
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Solution Overview
Problem
In NAND flash memory devices, high resistance in select gate lines leads to capacitive coupling with adjacent word lines, causing the select transistors to fail in cutting off the channel, resulting in leak currents and erroneous writing due to floating potential.
Innovation Solution
A semiconductor memory device configuration with serially connected memory cell transistors and select transistors, where the select gate lines are independently controlled by a row decoder to prevent voltage rise due to capacitive coupling, ensuring proper cut-off characteristics and preventing leak currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If select gate lines are shared/commonly controlled, then device complexity is reduced, but voltage control precision deteriorates due to capacitive coupling causing floating potential
Solution Approach 1:
The patent divides the select gate lines into two independent groups: first select gate lines (SGD1) connected to first word lines and second select gate lines (SGD2) connected to second word lines. This segmentation allows independent voltage control for each group, preventing capacitive coupling interference between adjacent word lines from affecting both select gate lines simultaneously. The row decoder applies different voltage patterns to SGD1 and SGD2 independently, resolving the voltage control precision issue while maintaining reasonable device complexity.
Solution Approach 2:
The patent applies different voltage control strategies to different regions of the memory device. First select gate lines receive one voltage pattern while second select gate lines receive another voltage pattern, tailored to their specific positional relationships with adjacent word lines. This local quality approach optimizes cut-off characteristics for each select gate line group based on their individual capacitive coupling conditions, improving overall voltage control precision without uniformly increasing device complexity.
2Device complexity
If select gate line resistance is high, then wiring complexity is reduced, but reliability deteriorates due to potential floating and leak current generation
Solution Approach 1:
The patent applies preliminary voltage control actions to select gate lines before word line voltage transitions occur. By pre-setting the voltage levels of first and second select gate lines according to the upcoming word line operations, the system prevents capacitive coupling from causing unintended potential floating. This preliminary action ensures select transistors maintain proper cut-off characteristics throughout word line voltage variations, improving reliability without requiring lower select gate line resistance or more complex wiring.
Solution Approach 2:
The patent implements preliminary anti-action by applying counteracting voltage patterns to select gate lines that anticipate and counterbalance the capacitive coupling effects from adjacent word lines. The row decoder generates voltage patterns for SGD1 and SGD2 that pre-compensate for the floating potential tendency, creating an opposing effect that cancels out the harmful capacitive coupling. This preliminary anti-action maintains reliable cut-off characteristics without modifying the physical wiring structure or resistance values.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The independent voltage control of select gate lines inhibits leak currents and erroneous writing, enhancing the reliability of NAND flash memory by improving the cut-off characteristics of select transistors.
Implementation Method 1
When resistance of the select gate line is high, potential of the select gate line floats up due to capacitive coupling with a word line adjacent to the select gate line
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes: a memory string including first and second select transistors and memory cell transistors; a bit line connected to the first select transistor; word lines which are connected to gates of the memory cell transistors, respectively; first and second select gate lines which are connected to gates of the first and second select transistors, respectively; a first contact plug connected to the first select gate line; a first wiring layer provided on the first contact plug; a second contact plug connected to the second select gate line; a second wiring layer provided on the second contact plug; and a row decoder connected to the first and second wiring layers. The row decoder applies different voltages to the first select gate line and the second select gate line.