NAND Flash Select Gate Voltage Control for Negative Threshold Cells
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Solution Overview
Problem
Current NAND flash memory technologies lack an effective method for controlling the select gate voltage during read and verify operations for cells with negative threshold voltages, which is crucial for stable data retrieval.
Innovation Solution
A voltage control circuit that applies a select gate voltage obtained by adding a biased positive voltage to the voltage set at read time for cells with positive threshold voltages to the select gate at read and verify times for cells with negative threshold voltages, with the voltage being raised in at least two separate steps to ensure stable operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the voltage of the select gate is set to 4V or more at the read time for cells with negative threshold voltages, then the read and verify operations can be performed, but the voltage control method is not yet provided and the operation stability is poor
Solution Approach 1:
The source line and well line are pre-biased to a positive voltage (e.g., 1V) before the read operation begins. This preliminary voltage biasing enables the subsequent read and verify operations for cells with negative threshold voltages to be performed stably, as the positive bias creates the necessary voltage conditions for reliable cell readout.
Solution Approach 2:
The voltage parameters of the source line and well line are changed from the conventional 0V to a positive voltage (e.g., 1V) during read operations. This parameter change fundamentally alters the voltage conditions in the memory cell, enabling stable read and verify operations for cells with negative threshold voltages by shifting the operating point to a region where reliable detection is possible.
2Productivity
If the voltage of the select gate is instantly raised to approximately 4V at the start time of the read operation, then the read operation can be initiated, but gate oxide films may be damaged and read disturb may occur
Solution Approach 1:
The source line and well line are pre-biased to a positive voltage before the read operation starts. This preliminary action creates a safer voltage environment that allows for more controlled voltage transitions, reducing the risk of gate oxide damage while still enabling efficient read operations.
Solution Approach 2:
By pre-biasing the source line and well line to a positive voltage, the system creates a cushioning effect that protects against voltage spikes and transient conditions that could damage gate oxide films. This prior cushioning allows the select gate voltage to be raised more safely during the read operation.
3Adaptability or versatility
If the voltage of the source line and well line are biased to a positive voltage at the read time, then the read and verify operations for cells with negative threshold voltages can be performed, but the select gate voltage control becomes more difficult
Solution Approach 1:
The source line and well line are pre-biased to a positive voltage before the read operation begins. This preliminary action simplifies the overall voltage control by establishing the necessary conditions in advance, making it easier to perform read and verify operations for cells with negative threshold voltages without complex real-time adjustments.
Solution Approach 2:
The positive voltage bias on the source line and well line acts as an intermediary that mediates between the control circuit and the memory cells with negative threshold voltages. This intermediary biasing simplifies the control interface by creating a standardized voltage environment that facilitates easier voltage management during read operations.
Data Source
AI summary
There is provided a nonvolatile semiconductor memory device which can read and verify a cell with a negative threshold voltage by biasing voltages of a source line and well line to a positive voltage. The nonvolatile semiconductor memory device includes a voltage control circuit which applies a select gate voltage obtained by adding the biased positive voltage to a voltage set at read time of a cell with a positive threshold voltage to a select gate at a read time and verify time for the cell with the negative threshold voltage.