NAND Flash Memory Controller for Select-Gate-Aware Data Writing
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Solution Overview
Problem
Conventional NAND flash memory systems experience reliability issues due to data loss and bit errors when writing important data, particularly system information, as the regularity of word lines and bit lines breaks near select gate lines, leading to defects.
Innovation Solution
A memory controller that selectively writes data by avoiding word lines and bit lines adjacent to select gate lines, using alternative modes such as binary or multilevel modes to reduce stress and improve data reliability, and applies these methods only to memory blocks with low reliability to efficiently use the memory cell array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is written using conventional word line selection methods in NAND flash memory, then writing speed is maintained, but reliability deteriorates due to data loss and bit errors near select gate lines
Solution Approach 1:
The patent applies local quality by differentiating the writing process based on location. When a word line adjacent to select gate lines is detected, the system switches to a specialized writing mode that avoids the defective regions. This localized adaptation ensures high reliability for data written in vulnerable areas while maintaining conventional efficient writing in safe areas, thus resolving the contradiction between reliability and write precision.
Solution Approach 2:
The patent changes the writing parameters dynamically based on the selected word line. When adjacent word lines are detected, it alters the write voltage, pulse width, or sequencing parameters to prevent data loss and bit errors. This parameter adaptation allows the system to maintain reliable writing in problematic regions without sacrificing overall writing efficiency, resolving the contradiction between reliability and write precision.
2Quantity of substance
If word lines adjacent to select gate lines are used for writing data, then memory capacity utilization is improved, but bit errors increase due to broken regularity of word and bit lines
Solution Approach 1:
The patent implements preliminary action by detecting which word lines are adjacent to select gate lines before the actual writing operation begins. This advance detection allows the system to prepare appropriate writing parameters or alternative storage locations, preventing data integrity issues before they occur. By taking this preliminary measure, the system can safely utilize more memory capacity while maintaining high data integrity.
Solution Approach 2:
The patent introduces an intermediary control mechanism that mediates between the desire to maximize memory capacity utilization and the need to ensure data integrity. This intermediary layer analyzes the memory map, identifies vulnerable regions, and routes writing operations appropriately - either using enhanced writing modes for adjacent word lines or redirecting to safer regions, thus reconciling capacity utilization with data integrity.
3Reliability
If conventional writing methods are used without considering select gate line proximity, then writing speed is maintained, but system reliability deteriorates due to data loss
Solution Approach 1:
The patent applies self-service by enabling the memory controller to automatically detect and handle problematic writing scenarios without external intervention. The system autonomously identifies when word lines adjacent to select gate lines are being used and self-adjusts the writing parameters or redirects operations accordingly. This self-service capability enhances system reliability while keeping the control logic integrated and manageable, rather than requiring complex external control mechanisms.
Solution Approach 2:
The patent implements feedback by continuously monitoring the writing operation status and detecting when adjacent word lines are involved. Based on this feedback, the system dynamically adjusts the writing strategy - either applying corrected writing sequences or selecting alternative storage locations. This feedback mechanism ensures high system reliability while maintaining relatively simple control structure, as the feedback is generated and processed within the existing memory controller architecture.
Data Source
AI summary
A memory controller for writing data in a first semiconductor memory including a plurality of memory cells having series-connected current paths and charge storage layers includes a host interface which configured to be receivable of first data from a host apparatus, a second semiconductor memory which temporarily holds second data, and an arithmetic unit which generates the second data in accordance with the state of the first semiconductor memory, temporarily holds the second data in the second semiconductor memory, and writes the first and second data in the first semiconductor memory. When writing the second data, the arithmetic unit does not select a word line adjacent to a select gate line, and selects a word line not adjacent to the select gate line.