NAND Flash Read Disturbance Mitigation via Selection Gate Voltage Control
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Solution Overview
Problem
Existing NAND type flash memory devices face challenges in minimizing read disturbance, particularly due to hot carriers injected into memory cells adjacent to selection gate lines in non-selected NAND strings.
Innovation Solution
The implementation involves applying a specific voltage to the selection gate lines of non-selected NAND strings during a read operation, which reduces the voltage difference between the selection gate line and adjacent word lines, thereby minimizing read disturbance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a read operation is performed on selected memory cells, then data can be retrieved, but hot carriers are injected into adjacent memory cells causing read disturbance
Solution Approach 1:
The patent applies preliminary anti-action by pre-charging selection gate lines to a first voltage level before the read operation begins. This preliminary voltage application creates a protective potential that counteracts the hot carrier injection effect during the read operation, preventing threshold voltage shifts in non-selected memory cells before the disturbance can occur
Solution Approach 2:
The patent utilizes parameter changes by dynamically adjusting the voltage levels on selection gate lines throughout the read operation. The selection gate lines transition from a first voltage level during programming to a second voltage level during verification, and then back to the first voltage level during subsequent read operations. This parameter modulation optimizes the electric field distribution to minimize hot carrier generation while maintaining read capability
2Reliability
If verification is performed after programming, then data accuracy can be confirmed, but additional time is required
Solution Approach 1:
The patent applies preliminary action by performing verification operations immediately after programming while the memory cells are still in a suitable state. The verification uses the same selection gate line voltage configuration as the programming operation, allowing for rapid confirmation of data accuracy without requiring additional voltage transitions or preparation steps that would consume extra time
Data Source
AI summary
A memory device includes a memory cell array having memory strings that include memory cells and first and second selection transistors. During a read operation, a controller applies a first voltage higher than ground to a source line, and a second voltage to a first and second selection gate lines that are connected to a selected memory string. The second voltage is also applied to the first selection gate lines connected to non-selected memory during a first period of the read operation. A third voltage higher than ground and lower than the second voltage is applied to the first selection gate lines connected to non-selected memory strings during a second period of the read operation subsequent to the first period.