NAND Flash Storage Self-Testing for Bad Block Detection
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Solution Overview
Problem
Testing defective blocks in NAND flash memory devices is computationally intensive and resource-consuming, requiring multiple loops for programming, reading, and verifying data, which strains the host's computations, DRAM space, and bus bandwidth.
Innovation Solution
A method and apparatus for testing storage units using a processing unit that receives a test write command, programs and reads test patterns into a Physical Block Address (PBA), and generates a test message based on the results, reducing the need for extensive host involvement through the use of a test writer and test reader with error correction and detection mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the host performs extensive programming, reading, and verification loops to test all defective blocks in NAND flash memory, then the reliability of defect detection is improved, but the consumption of host computations, DRAM space, and bus bandwidth increases excessively
Solution Approach 1:
The patent introduces an intermediary testing mechanism where the storage unit itself performs self-testing operations. The processing unit within the storage device executes test patterns and generates test results locally, acting as a mediator between the host and the memory cells. This eliminates the need for the host to perform exhaustive testing loops, thereby reducing host resource consumption while maintaining defect detection reliability.
Solution Approach 2:
The storage unit performs self-testing through integrated test writers and test readers that operate autonomously within the device. The processing unit generates test patterns, programs them into memory blocks, reads back the data, and verifies integrity without requiring continuous host intervention. This self-service approach shifts the testing burden from the host to the storage device itself, resolving the contradiction between reliable defect detection and host resource consumption.
2Reliability
If multiple loops for programming, reading, and verifying each NAND page are executed to identify all bad blocks, then the completeness of defect identification is improved, but the testing time and computational overhead increase significantly
Solution Approach 1:
The patent implements preliminary testing actions by executing test patterns on memory blocks before they are fully integrated into normal operation. The test writer pre-programs test data into candidate blocks, and the test reader pre-verified them for defects. This preliminary action identifies bad blocks early in the process, eliminating the need for multiple subsequent verification loops and reducing overall testing time while maintaining completeness.
Solution Approach 2:
The system employs feedback mechanisms where test results are immediately processed and used to determine subsequent testing actions. The processing unit analyzes test results from the test reader and dynamically adjusts the testing process, skipping already-verified good blocks and focusing resources on uncertain cases. This feedback-driven approach reduces redundant testing iterations while ensuring all defective blocks are identified.
3Measurement precision
If the host directly tests all memory blocks in NAND flash devices, then the accuracy of bad block detection is improved, but the device complexity and host involvement required increase
Solution Approach 1:
The patent merges the testing functions with the existing storage device architecture by integrating test writers, test readers, and processing units within the storage device itself. Rather than separating testing as an external host-only function, the system combines testing capabilities with normal storage operations. This merging maintains detection accuracy while reducing device complexity by eliminating the need for separate external testing equipment and reducing host involvement.
Data Source
AI summary
The invention introduces a method for testing a storage unit, performed by a processing unit, including at least the following steps: after receiving a test write command from a host device through a first access interface, directing a second access interface to receive a first test pattern from a test writer and program the first test pattern into a PBA (Physical Block Address) of a storage unit; directing the second access interface to read a second test pattern from the PBA of the storage unit and output the second test pattern to a test reader; receiving a test result from the test reader; and generating a test message according to the test result and replying with the test message to the host device.