NAND Flash Memory Page Buffer for Low-Latency SFDP Data Access

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Solution Overview

Problem

NAND flash memories with SPI function face challenges in reading serial flash discoverable parameter (SFDP) data without latency, differing from NOR flash memories which can read such data quickly and synchronously with a short access delay.

Innovation Solution

The implementation of a page buffer with a first and second data keeping part in NAND flash memory, where parameter data is stored in areas not accessible to users, allowing for controlled reading based on input commands and external clocks, enabling efficient transfer and output of SFDP data without latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If NAND flash memory reads SFDP data from memory array using conventional method, then data accuracy is ensured, but reading speed is slow with significant latency

Engineering Contradiction:

ImproveSFDP data reading speedVSAvoidAccess delay time

Core Design Contradiction:

SpeedVSLoss of time

Solution Approach 1:

The patent pre-loads SFDP data from the memory array into the page buffer during power-on or reset, before any read commands are executed. This preliminary action ensures that when SFDP data is requested, it is already available in the page buffer, eliminating the need to read from the slower memory array at the moment of request, thus reducing access delay time while maintaining data accuracy

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent introduces the page buffer as an intermediary component between the memory array and the output interface. The page buffer acts as a high-speed cache that temporarily holds SFDP data, allowing fast retrieval without directly accessing the slower memory array, thereby improving reading speed while ensuring data integrity through the buffer's controlled transfer mechanism

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If NAND flash memory uses redundant memory and ECC circuits to repair physical flaws, then reliability is improved, but device complexity increases

Engineering Contradiction:

ImproveMemory device reliabilityVSAvoidRedundant scheme complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the SFDP data reading function from the main memory array access path and handles it separately through the page buffer. By isolating the parameter data reading operation, the system can use the existing redundant memory and ECC circuits for normal data operations without adding extra complexity specifically for SFDP data access, maintaining reliability while avoiding unnecessary complexity multiplication

Inventive Principle:

Principle #2Taking out (Extraction)

Data Source

PatentUS10957415B2NAND flash memory and reading method thereof

Publication Date: 2021.03.23 WINBOND ELECTRONICS CORP

AI summary

An NAND flash memory and a reading method thereof capable of high-speed reading of SFDP data are provided. The flash memory includes a memory cell array, a page buffer/reading circuit 170 and a controller 150. The page buffer/reading circuit 170 includes a first latch circuit L1 and a second latch circuit L2. The first latch circuit L1 keeps data read from the memory cell array. The second latch circuit L2 keeps data transferred from the first latch circuit L1. Just after power is turned on or reset, the controller 150 controls data of block 0/page 0 of the memory cell array to be kept in the second latch circuit L2 and controls the SFDP data to be kept in the first latch circuit L1. The SFDP data or the data of block 0/page 0 is serially output according to an input command.