NAND Flash Memory Plane Layout with Shared Transfer Transistors
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Solution Overview
Problem
The challenge in NAND type flash memory is to increase memory capacity without degrading chip performance, as finer memory cells lead to thinned and lengthened word lines, requiring division into multiple memory planes, which increases the number of row decoders and enlarges the chip area.
Innovation Solution
A floor plan layout is implemented where transfer transistors are shared across memory planes to reduce the number of row decoders, with drivers controlling time constants to equalize potential transfer rates across word lines, thereby maintaining performance without enlarging the chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are fabricated more finely to increase memory capacity, then memory capacity increases, but word lines become thinned and lengthened causing chip performance degradation
Solution Approach 1:
The memory cell array is divided into multiple memory planes (first memory plane and second memory plane), each with its own row decoder. This segmentation shortens the word line length within each plane, preventing performance degradation while maintaining increased memory capacity through finer cell fabrication.
2Reliability
If one memory cell array is divided into plural memory planes to shorten the word line, then chip performance is maintained, but the number of row decoders increases causing chip area enlargement
Solution Approach 1:
The first and second row decoders are positioned adjacent to each other and share a common potential transfer line. This merging approach allows multiple memory planes to be supported while reducing the total chip area by eliminating redundant potential transfer infrastructure.
Solution Approach 2:
The common potential transfer line serves both the first memory plane and the second memory plane, allowing a single infrastructure to support multiple row decoders and memory planes, thereby reducing overall chip area while maintaining performance.
3Adaptability or versatility
If the number of row decoders increases to support more memory planes, then word line control is improved, but chip area enlarges
Solution Approach 1:
Multiple row decoders are positioned adjacent to each other and share a common potential transfer line, merging infrastructure resources to reduce chip area while maintaining the ability to control multiple memory planes independently.
Solution Approach 2:
The common potential transfer line acts as an intermediary shared resource between multiple row decoders, enabling efficient resource utilization and reducing the total area required for supporting multiple memory planes.
Data Source
AI summary
According to one embodiment, a NAND type flash memory includes a first transfer transistor disposed between first and second memory planes, the first potential transfer terminal of the first transfer transistor being commonly connected to a first word line in the first NAND block and a second word line in the third NAND block, a second transfer transistor disposed at a first end of the first memory plane, the first potential transfer terminal of the second transfer transistor being connected to a third word line in the second NAND block, and a third transfer transistor disposed at a second end of the second memory plane, the first potential transfer terminal of the third transfer transistor being connected to a fourth word line in the fourth NAND block.