NAND Flash Memory Shielding Cells Reduce Programming Disturbance
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Solution Overview
Problem
Flash memory devices, particularly those with NAND architecture, face issues with 'Source/Drain Hot-Carrier Injection Disturbance' (SDHCID) that cause unintended charge injection into floating gates, leading to threshold voltage shifts and data corruption, especially in multi-level cells where margin for error is reduced.
Innovation Solution
Incorporating auxiliary shielding memory cells between the source select transistor and the first memory cell, and between the last memory cell and the drain select transistor, to act as shields and mitigate electric field effects that cause SDHCID, thereby protecting unselected memory cells from programming disturbances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high programming voltage is applied to control gate during programming operation, then programming speed and efficiency are improved, but unintended charge injection into unselected memory cells occurs causing data corruption
Solution Approach 1:
The patent introduces select transistor gate electrodes as intermediary elements between the programming voltage applied to the control gate and the floating gates of memory cells. By controlling the voltage potential of these gate electrodes during programming operations, the patent mediates the electric field distribution to prevent direct charge injection into unselected memory cells while allowing efficient programming of selected cells.
Solution Approach 2:
The patent applies different voltage potentials to different gate electrodes locally during programming operations. The control gate receives high programming voltage (e.g., 18V) for efficient programming, while select transistor gate electrodes are maintained at specific voltages (e.g., 0V or negative voltages) to locally suppress electric fields that would cause charge injection into unselected cells. This localized voltage control enables high-speed programming without compromising data integrity.
2Reliability
If distance between source select transistor and memory cells is increased to reduce electric field effects, then programming disturbance is reduced, but device area increases
Solution Approach 1:
The patent introduces select transistor gate electrodes as intermediary structures between the source/drain select transistors and the memory cell arrays. These gate electrodes act as voltage control barriers that mitigate electric field effects without requiring increased physical distance. By applying appropriate voltages to these gate electrodes, the patent reduces programming disturbance to unselected cells while maintaining compact device geometry.
Solution Approach 2:
The patent changes the voltage parameter of select transistor gate electrodes during programming operations to control electric field distribution. Instead of relying on physical distance, the patent dynamically adjusts voltage potentials (e.g., setting gate electrodes to 0V or negative voltages during programming) to reduce electric field strength and prevent charge injection into unselected memory cells, thereby reducing programming disturbance without increasing device area.
3Productivity
If voltage difference between control gate and drain terminal is increased to improve programming efficiency, then programming speed increases, but charge injection disturbance into unselected cells increases
Solution Approach 1:
The patent introduces select transistor gate electrodes as intermediary elements that control the voltage potential distribution between the control gate and drain terminal during programming. By adjusting the voltage of these gate electrodes, the patent mediates the electric field to maintain high voltage difference for efficient programming while preventing excessive electric fields that would cause charge injection into unselected cells.
Solution Approach 2:
The patent applies different voltage potentials locally to different gate electrodes during programming. The control gate is biased at high voltage (e.g., 18V) for efficient programming, while select transistor gate electrodes are biased at specific voltages (e.g., 0V or negative) to locally suppress electric fields near unselected memory cells. This local voltage differentiation enables high programming efficiency while minimizing charge injection disturbance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The introduction of shielding memory cells significantly reduces or eliminates SDHCID, ensuring accurate data storage and retrieval by preventing unwanted charge injection, without significantly increasing the size of the memory device.
Implementation Method 1
each one having a programmable threshold voltage in response to an electric field applied between a control gate and a bulk terminal
Implementation Method 2
Source/Drain Hot-Carrier Injection Disturbance (SDHCID) that cause unintended charge injection into floating gates
Implementation Method 3
each memory cell consists of a floating-gate MOS transistor, which stores a logic value defined by its threshold voltage (which depends on the electric charge stored on the floating gate)
Implementation Method 4
during the programming of the floating-gate MOS transistor, electrons are injected, for example, by means of the known Fowler-Nordheim mechanism, into the floating gate
Data Source
AI summary
An embodiment of a flash memory device with NAND architecture, including a matrix of data storage memory cells each one having a programmable threshold voltage, wherein the matrix is arranged in a plurality of rows and columns with the memory cells of each row being connected to a corresponding word line and the memory cells of each column being arranged in a plurality of strings of memory cells, the memory cells in each string being connected in series, the strings of each column being coupled to a reference voltage distribution line distributing a reference voltage by means of a first selector, wherein each string further includes at least one first shielding element interposed between the memory cells of the string and said first selector, the first shielding element being adapted to shield the memory cells from electric fields that, in operation, arise between the string of memory cells and the first selector.