NAND Flash Short-Checking Method for Defect Isolation
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Solution Overview
Problem
NAND flash memory devices face issues with shorts occurring between the control gate and semiconductor, leading to failed bits and uncorrectable bit code errors due to defects in dielectric layers, which are not effectively identified by existing technologies.
Innovation Solution
Implementing a short-checking method within the memory device's control logic that involves charging a data line to an initial voltage, allowing it to float while activating memory cells, and sensing the resulting voltage to determine if a short exists, thereby identifying and tagging defective blocks during normal operation or test modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If existing short-checking methods are used, then manufacturing process is simple, but shorts between word lines and semiconductors are not effectively identified
Solution Approach 1:
The patent applies preliminary action by performing short detection during the erase operation sequence before the memory block is made available for normal use. The method proactively identifies shorts between word lines and semiconductors by charging bit lines to a first voltage, activating memory cells, and sensing voltage levels that indicate the presence of shorts, thereby preventing failed bits from occurring in the first place
Solution Approach 2:
The patent uses the bit line voltage as an intermediary indicator to detect shorts. By charging the bit line to a known voltage and then sensing whether that voltage is maintained (indicating no short) or discharged (indicating a short to semiconductor), the method indirectly detects the presence of shorts without requiring direct measurement of the defect itself
2Reliability
If no short-checking is performed, then device operation is fast, but failed bits and uncorrectable errors occur
Solution Approach 1:
The patent merges the short detection function with the existing erase operation sequence. The short-checking method is integrated into the normal memory operation flow by combining the bit line charging and sensing steps with the erase verify process, so that short detection occurs as part of the routine erase operation rather than as a separate additional step
Solution Approach 2:
The memory device performs self-diagnosis by using its own existing circuitry (bit lines, sense amplifiers, control logic) to detect shorts during normal operation. The system serves itself by identifying and tagging defective blocks without requiring external testing equipment, thereby maintaining reliability while minimizing impact on operation speed
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Effectively identifies shorts between word lines and semiconductors, preventing failed bits and reducing uncorrectable bit code errors by isolating and removing defective blocks, thus enhancing the reliability of NAND flash memory devices.
Implementation Method 1
charging a data line to an initial voltage, allowing it to float while activating memory cells
Implementation Method 2
sensing the resulting voltage to determine if a short exists
Data Source
AI summary
In an embodiment, a short-checking method includes charging a data line to an initial voltage while activating a memory cell coupled to the data line, allowing the data line to float while continuing to activate the memory cell, sensing a resulting voltage on the data line after a certain time, and determining whether a short exists in response to a level of the resulting voltage.