NAND Flash Memory Signal Integrity Test via Buffer Segmentation
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Solution Overview
Problem
The increasing operating speed of NAND flash memory interfaces necessitates evaluating signal integrity, which is challenging due to the inability to distinguish between interface signal integrity issues and memory cell characteristics, as data read from NAND flash memory may contain errors, making it difficult to perform accurate signal integrity tests without error correction.
Innovation Solution
A semiconductor memory device with a memory cell array, buffers, and an interface unit, where data is transferred and verified without writing to the memory cell array, using test sequences and cache operations to evaluate the signal integrity of the high-speed interface without relying on memory cell data reliability, allowing for precise evaluation of signal integrity in the package/board.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If data is read from the memory cell array for testing, then the test can be performed using existing memory structure, but the data reliability is compromised due to memory cell errors
Solution Approach 1:
The patent segments the data path into two independent channels: one for writing test data to the memory cell array and another for reading reference data. By separating the test data flow from the memory cell data flow, the system can compare interface-transferred data against known-good reference data, thereby isolating interface signal integrity issues from memory cell errors.
Solution Approach 2:
The patent introduces a reference data path as an intermediary that provides a reliable data source. This reference path bypasses the memory cell array's error-prone data path and provides clean reference data for comparison, enabling accurate signal integrity testing without being affected by memory cell characteristics.
2Speed
If the operating speed is increased for high-speed interface, then the interface performance is improved, but the signal integrity becomes difficult to evaluate
Solution Approach 1:
The patent performs preliminary actions by writing known test data patterns to the memory cell array before the actual signal integrity test. This pre-loaded reference data serves as a baseline for comparison during high-speed interface testing, enabling accurate evaluation of signal integrity even at increased operating speeds.
Solution Approach 2:
The patent implements a feedback mechanism by comparing the data transferred through the high-speed interface with the reference data stored in the memory cell array. This comparison provides feedback on signal integrity, allowing the system to evaluate whether data transmission errors are caused by interface issues rather than memory cell characteristics.
3Reliability
If error correction is used to handle memory cell errors, then data reliability is improved, but the ability to distinguish interface issues from memory cell issues is lost
Solution Approach 1:
The patent extracts the reference data path from the main data flow to create a separate comparison channel. By taking out the reference data reading path and comparing it independently with the interface-transferred data, the system can identify interface-specific errors without the confounding effect of memory cell errors that would be present in the main data path.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes a memory cell array, a first buffer, a second buffer, an interface unit and a controller. Data is transferred between the interface unit and the first buffer. The controller controls the first buffer, the second buffer and the interface unit. When receiving a first command and first data at a test time, the controller transfers the first data to the first buffer via the interface unit. When receiving a second command as a dummy command, the controller reads second data from the memory cell array to the second buffer and, at the same time, outputs first data held in the first buffer via the interface unit.