NAND Flash Memory Controller SLC Buffer Management
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Solution Overview
Problem
The existing memory systems using nonvolatile semiconductor memory elements face performance degradation when the SLC buffer region is fully utilized, leading to reduced write performance from the host device's perspective, as data must be written directly to the multi-value region without utilizing the SLC buffer region.
Innovation Solution
A memory system that includes a controller which writes 1-bit data to an SLC buffer region, compresses and writes unit data to a compressed-data region, and then decompresses and writes it to a multi-value region, thereby maintaining a free area in the SLC buffer region and improving write performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is written to the SLC buffer region using the SLC method, then write performance is improved, but the free area of the SLC buffer region is reduced
Solution Approach 1:
The patent divides the NAND flash memory into multiple regions including an SLC buffer region and a multi-value region, allowing data to be segmented and written to different regions based on availability. When the SLC buffer region is full, data is written to the multi-value region instead, preventing performance degradation while maintaining the benefits of SLC buffering when available.
Solution Approach 2:
The patent implements dynamic write strategy that adapts based on the free area of the SLC buffer region. The controller monitors the buffer status and dynamically switches between writing to the SLC buffer region (when free area is sufficient) and writing directly to the multi-value region (when buffer is full), optimizing write performance under varying conditions.
2Area of stationary object
If data is written directly to the multi-value region without using the SLC buffer region, then the free area of the SLC buffer region is maintained, but write performance is degraded
Solution Approach 1:
The patent segments the write destination into two paths: one through the SLC buffer region for high-performance writes when buffer space is available, and another directly to the multi-value region when the buffer is full. This segmentation allows the system to maintain buffer free area while preventing performance degradation by providing an alternative write path.
Solution Approach 2:
The patent changes the write destination parameter dynamically based on the free area of the SLC buffer region. When the buffer is full, the system changes from buffer-mediated writing to direct writing, adjusting the operational parameter to match current buffer status and maintain optimal performance.
3Quantity of substance
If the SLC buffer region is fully utilized, then data storage capacity is increased, but write performance from the host device's perspective is reduced
Solution Approach 1:
The patent segments the storage system into an SLC buffer region for high-speed temporary storage and a multi-value region for permanent storage. When the SLC buffer region is fully utilized, the system segments the write operation to use the multi-value region as an additional storage path, maintaining both storage capacity and write performance.
Solution Approach 2:
The patent uses the multi-value region as an intermediary storage path when the SLC buffer region is full. Instead of rejecting writes or significantly degrading performance, the system routes excess data through the multi-value region, which acts as a mediator to maintain write performance while utilizing available storage capacity.
Data Source
AI summary
According to one embodiment, a memory system includes a NAND flash memory that has a first area, a second area, and a third area, and a controller that controls data transfer between a host device and the memory system. The controller writes data transmitted from the host device to the first area by a first method of storing 1-bit data per memory cell, and at a first timing, reads at least a part of data stored in the first area to generate one unit data, compresses the unit data, and writes the compressed unit data to the second area. At a second timing, the controller decompresses the read compressed unit data from the second area, and writes the decompressed unit data to the third area by a second method of storing a plurality of bits of data per memory cell.