NAND Flash Soft-Decision Compression for Accurate Data Reads
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Solution Overview
Problem
Traditional NAND flash memory devices face challenges in accurately reading data over time due to the coarse discrimination of cell voltage as either 0 or 1, leading to errors in data retrieval.
Innovation Solution
The introduction of soft decision technology, which analyzes voltage more finely and estimates the probability of its corresponding value, enhances the performance of error correction codes and extends the lifespan of NAND flash memory devices. This is achieved through a nonvolatile memory device with a compression circuit that reads soft decision data, compresses it, and overwrites the compressed data, utilizing two separate address controllers for read and write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If soft decision technology is introduced to improve data reading accuracy, then the measurement precision of voltage analysis is improved, but the device complexity increases due to the need for compression circuits and separate address controllers
Solution Approach 1:
The patent merges the compression circuit functionality directly into the nonvolatile memory device structure, integrating the encoder and buffer with the existing latch groups. This consolidation achieves data compression to reduce bitwidth while maintaining soft decision accuracy, thereby improving measurement precision without proportionally increasing device complexity through separate standalone components
Solution Approach 2:
The latch groups in the nonvolatile memory device are designed to serve multiple functions: they store both raw soft decision data and compressed data, and can be controlled by different address controllers for different operations. This multi-functionality allows the same hardware structure to support both high-precision voltage analysis and data compression, reducing the need for additional dedicated components
2Quantity of substance
If compression circuit is added to reduce storage capacity requirements, then the quantity of substance for storage is reduced, but the device complexity increases due to additional encoding and buffer components
Solution Approach 1:
The patent implements a nested structure where the buffer is integrated within the nonvolatile memory device architecture, and the encoder processes data that is subsequently stored in the same device's latch groups. This nesting allows compression functionality to be embedded within the existing storage structure, reducing the effective storage capacity needed while avoiding the overhead of completely separate compression hardware systems
Solution Approach 2:
The nonvolatile memory device performs compression of its own stored data through the integrated encoder, and the buffer manages its own data flow between the encoder and latch groups. This self-service capability allows the device to reduce its own storage requirements without requiring external compression hardware, thereby reducing the quantity of storage substance needed while minimizing additional device complexity
3Ease of operation
If separate address controllers are used for read and write operations, then the ease of operation is improved through independent control, but the device complexity increases due to dual address control architecture
Solution Approach 1:
The patent segments the address control functionality into two independent controllers: one dedicated to read operations and another dedicated to write operations. This segmentation allows each controller to be optimized for its specific function, improving ease of operation through independent control of data input and output processes, while the modular nature of the segmentation keeps the added complexity manageable and well-organized
Data Source
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AI summary
A nonvolatile memory device includes a plurality of latch groups, an address controller, an encoder, and a buffer. The address controller controls an input address and an output address to indicate one of the plurality of latch groups. The encoder receives sector data from a latch group corresponding to the output address among the plurality of latch groups and also compresses the received sector data. The buffer stores the compressed sector data. Among the plurality of latch groups, the compressed sector data stored in the buffer is overwritten in a latch group corresponding to the input address.