Adaptive NAND Flash Reads for Soft-Decision Error Correction

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Solution Overview

Problem

As the feature size of NAND flash chips decreases, accurate information storage becomes challenging due to reduced electron capacity and increased inter-cell interference, leading to a low signal-to-noise ratio and high bit error rates, particularly in high-capacity multi-level cell storage, which degrades performance and requires multiple reads that can further degrade flash memory performance.

Innovation Solution

An adaptive multiple-read system for NAND flash memory that employs soft decision error correction using lookup tables containing log likelihood ratios, performing multiple read operations at different reference voltages until successful decoding is achieved, thereby enhancing error correction without incurring a performance penalty from unnecessary reads.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple read operations are performed to improve error correction in high-capacity NAND flash, then error correction performance is improved, but flash memory performance degrades due to unnecessary reads

Engineering Contradiction:
Improveerror correction performanceVSAvoidflash memory performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies parameter changes by performing read operations at multiple different reference voltages (e.g., first reference voltage, second reference voltage) to obtain different raw data words. This allows the system to gather diverse information about the stored data state, improving error correction capability without requiring excessive reads at the same voltage level.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The system uses the raw data words obtained from reads at different reference voltages to self-correct errors through the error correction code decoding process. By leveraging the complementary information from multiple voltage readings, the system can achieve reliable error correction while minimizing the total number of read operations needed.

Inventive Principle:
Principle #25Self-service

2Quantity of substance

If feature size of NAND flash chips is decreased to increase storage capacity, then storage density is improved, but signal-to-noise ratio decreases and bit error rate increases

Engineering Contradiction:
Improvestorage capacityVSAvoidsignal-to-noise ratio
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent addresses the degraded signal-to-noise ratio in high-density NAND flash by performing read operations at multiple reference voltage levels. This parameter variation approach allows the system to overcome the increased bit error rates caused by smaller feature sizes and inter-cell interference, extracting reliable data information despite the noisy environment.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The error correction code decoding process acts as an intermediary that processes the noisy raw data words obtained from reads at different reference voltages. This intermediary processing layer transforms the unreliable individual readings into accurate decoded data, compensating for the poor signal-to-noise ratio inherent in high-capacity NAND flash.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Measurement precision

If multiple read operations are performed to achieve accurate data retrieval, then data accuracy is improved, but read time increases

Engineering Contradiction:
Improvedata accuracyVSAvoidread time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent achieves accurate data retrieval by performing read operations at multiple reference voltages rather than performing many reads at a single voltage. This approach obtains complementary information more efficiently, allowing the error correction decoder to succeed with fewer total read operations, thus reducing the time loss while maintaining high data accuracy.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10417087B2System and method for adaptive multiple read of NAND flash
Publication Date: 2019.09.17 NETLIST INC
  • US10417087B2 patent drawing
  • US10417087B2 patent drawing
  • US10417087B2 patent drawing

AI summary

A system and method for adaptive multiple read of NAND flash memory. A solid state drive may employ adaptive multiple-read to perform enhanced performance error correction using soft decisions without a performance penalty that otherwise might result from performing unnecessary reads. The soft decision error correcting algorithm may employ lookup tables containing log likelihood ratios. The method may include performing one or more read operations to obtain one or more raw data words for a code word, attempting to decode the code words using the one or more raw data words, and performing additional read operations when the decoding attempt fails. This process may be repeated until a decoding attempt succeeds.